diff -urN linux-2.4.21-rmk2.orig/arch/arm/config.in linux-2.4.21-rmk2/arch/arm/config.in --- linux-2.4.21-rmk2.orig/arch/arm/config.in Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/arch/arm/config.in Mon Mar 8 14:27:28 2004 @@ -144,6 +144,7 @@ mainmenu_option next_comment comment 'AT91RM9200 Implementations' dep_bool ' Atmel AT91RM9200 Development Board' CONFIG_ARCH_AT91RM9200DK $CONFIG_ARCH_AT91RM9200 +dep_bool ' Cogent CSB337' CONFIG_MACH_CSB337 $CONFIG_ARCH_AT91RM9200 endmenu mainmenu_option next_comment @@ -540,7 +541,8 @@ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \ "$CONFIG_ARCH_CDB89712" = "y" -o \ "$CONFIG_ARCH_P720T" = "y" -o \ - "$CONFIG_ARCH_OMAHA" = "y" ]; then + "$CONFIG_ARCH_OMAHA" = "y" -o \ + "$CONFIG_ARCH_AT91RM9200" = "y" ]; then bool 'Timer and CPU usage LEDs' CONFIG_LEDS if [ "$CONFIG_LEDS" = "y" ]; then if [ "$CONFIG_ARCH_NETWINDER" = "y" -o \ @@ -550,7 +552,8 @@ "$CONFIG_ARCH_SA1100" = "y" -o \ "$CONFIG_ARCH_INTEGRATOR" = "y" -o \ "$CONFIG_ARCH_P720T" = "y" -o \ - "$CONFIG_ARCH_OMAHA" = "y" ]; then + "$CONFIG_ARCH_OMAHA" = "y" -o \ + "$CONFIG_ARCH_AT91RM9200" = "y" ]; then bool ' Timer LED' CONFIG_LEDS_TIMER bool ' CPU usage LED' CONFIG_LEDS_CPU fi diff -urN linux-2.4.21-rmk2.orig/arch/arm/def-configs/at91rm9200dk linux-2.4.21-rmk2/arch/arm/def-configs/at91rm9200dk --- linux-2.4.21-rmk2.orig/arch/arm/def-configs/at91rm9200dk Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/arch/arm/def-configs/at91rm9200dk Mon Mar 8 14:27:28 2004 @@ -111,6 +111,7 @@ # AT91RM9200 Implementations # CONFIG_ARCH_AT91RM9200DK=y +# CONFIG_MACH_CSB337 is not set # # CLPS711X/EP721X Implementations @@ -125,6 +126,7 @@ # CONFIG_ARCH_EP7211 is not set # CONFIG_ARCH_EP7212 is not set # CONFIG_ARCH_ACORN is not set +# CONFIG_PLD is not set # CONFIG_FOOTBRIDGE is not set # CONFIG_FOOTBRIDGE_HOST is not set # CONFIG_FOOTBRIDGE_ADDIN is not set @@ -135,9 +137,10 @@ # CONFIG_CPU_ARM720T is not set CONFIG_CPU_ARM920T=y # CONFIG_CPU_ARM922T is not set -# CONFIG_PLD is not set # CONFIG_CPU_ARM926T is not set # CONFIG_CPU_ARM1020 is not set +# CONFIG_CPU_ARM1020E is not set +# CONFIG_CPU_ARM1022 is not set # CONFIG_CPU_ARM1026 is not set # CONFIG_CPU_SA110 is not set # CONFIG_CPU_SA1100 is not set @@ -164,6 +167,7 @@ # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set # CONFIG_FPE_FASTFPE is not set CONFIG_KCORE_ELF=y # CONFIG_KCORE_AOUT is not set @@ -173,6 +177,9 @@ # CONFIG_PM is not set # CONFIG_ARTHUR is not set CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20210000,3145728 root=/dev/ram rw" +CONFIG_LEDS=y +CONFIG_LEDS_TIMER=y +# CONFIG_LEDS_CPU is not set CONFIG_ALIGNMENT_TRAP=y # @@ -204,6 +211,7 @@ # CONFIG_MTD_CFI_ADV_OPTIONS is not set # CONFIG_MTD_CFI_INTELEXT is not set CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set @@ -230,7 +238,9 @@ # CONFIG_MTD_AUTCPU12 is not set # CONFIG_MTD_EDB7312 is not set # CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_CEIVA is not set # CONFIG_MTD_PCI is not set +# CONFIG_MTD_PCMCIA is not set # # Self-contained MTD device drivers @@ -250,9 +260,9 @@ # NAND Flash Device Drivers # CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_ECC=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set -CONFIG_MTD_AT91_SMARTMEDIA=y +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_AT91_SMARTMEDIA is not set # # Plug and Play configuration @@ -276,6 +286,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_STATS is not set # # Multi-device support (RAID and LVM) @@ -382,10 +393,12 @@ # # CONFIG_ACENIC is not set # CONFIG_DL2K is not set +# CONFIG_E1000 is not set # CONFIG_MYRI_SBUS is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set # CONFIG_FDDI is not set @@ -456,6 +469,7 @@ # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_MX1TS is not set # # Character devices @@ -529,6 +543,11 @@ # # CONFIG_INPUT_GAMEPORT is not set # CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMI_PANIC_EVENT is not set +# CONFIG_IPMI_DEVICE_INTERFACE is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_IPMI_WATCHDOG is not set # # Watchdog Cards @@ -537,12 +556,14 @@ CONFIG_WATCHDOG_NOWAYOUT=y # CONFIG_ACQUIRE_WDT is not set # CONFIG_ADVANTECH_WDT is not set +# CONFIG_ALIM1535_WDT is not set # CONFIG_ALIM7101_WDT is not set # CONFIG_SC520_WDT is not set # CONFIG_PCWATCHDOG is not set # CONFIG_21285_WATCHDOG is not set # CONFIG_977_WATCHDOG is not set # CONFIG_SA1100_WATCHDOG is not set +# CONFIG_EPXA_WATCHDOG is not set # CONFIG_OMAHA_WATCHDOG is not set CONFIG_AT91_WATCHDOG=y # CONFIG_EUROTECH_WDT is not set @@ -552,11 +573,15 @@ # CONFIG_MIXCOMWD is not set # CONFIG_60XX_WDT is not set # CONFIG_SC1200_WDT is not set +# CONFIG_SCx200_WDT is not set # CONFIG_SOFT_WATCHDOG is not set # CONFIG_W83877F_WDT is not set # CONFIG_WDT is not set # CONFIG_WDTPCI is not set # CONFIG_MACHZ_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_SCx200_GPIO is not set +# CONFIG_AMD_PM768 is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set CONFIG_AT91_RTC=y @@ -589,6 +614,8 @@ # CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set # CONFIG_BFS_FS is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set @@ -606,6 +633,9 @@ # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set # CONFIG_NTFS_FS is not set @@ -636,6 +666,7 @@ # CONFIG_ROOT_NFS is not set # CONFIG_NFSD is not set # CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set # CONFIG_SUNRPC is not set # CONFIG_LOCKD is not set # CONFIG_SMB_FS is not set @@ -649,7 +680,6 @@ # CONFIG_NCPFS_NLS is not set # CONFIG_NCPFS_EXTRAS is not set # CONFIG_ZISOFS_FS is not set -# CONFIG_ZLIB_FS_INFLATE is not set # # Partition Types @@ -675,7 +705,6 @@ # CONFIG_USB_DEBUG is not set # CONFIG_USB_DEVICEFS is not set # CONFIG_USB_BANDWIDTH is not set -# CONFIG_USB_LONG_TIMEOUT is not set # CONFIG_USB_EHCI_HCD is not set # CONFIG_USB_UHCI is not set # CONFIG_USB_UHCI_ALT is not set @@ -685,6 +714,7 @@ # CONFIG_USB_AUDIO is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_BLUETOOTH is not set +# CONFIG_USB_MIDI is not set # CONFIG_USB_STORAGE is not set # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set @@ -693,6 +723,7 @@ # CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_HP8200e is not set # CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set @@ -701,7 +732,10 @@ # CONFIG_USB_HIDDEV is not set # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set # CONFIG_USB_WACOM is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set # CONFIG_USB_DC2XX is not set # CONFIG_USB_MDC800 is not set # CONFIG_USB_SCANNER is not set @@ -719,35 +753,11 @@ # USB Serial Converter support # # CONFIG_USB_SERIAL is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set -# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_TIGL is not set # CONFIG_USB_BRLVGER is not set +# CONFIG_USB_LCD is not set # # Bluetooth support @@ -771,3 +781,9 @@ CONFIG_DEBUG_LL=y # CONFIG_DEBUG_DC21285_PORT is not set # CONFIG_DEBUG_CLPS711X_UART2 is not set + +# +# Library routines +# +# CONFIG_ZLIB_INFLATE is not set +# CONFIG_ZLIB_DEFLATE is not set diff -urN linux-2.4.21-rmk2.orig/arch/arm/def-configs/csb337 linux-2.4.21-rmk2/arch/arm/def-configs/csb337 --- linux-2.4.21-rmk2.orig/arch/arm/def-configs/csb337 Thu Jan 1 02:00:00 1970 +++ linux-2.4.21-rmk2/arch/arm/def-configs/csb337 Mon Mar 8 14:27:28 2004 @@ -0,0 +1,732 @@ +# +# Automatically generated by make menuconfig: don't edit +# +CONFIG_ARM=y +# CONFIG_EISA is not set +# CONFIG_SBUS is not set +# CONFIG_MCA is not set +CONFIG_UID16=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +# CONFIG_GENERIC_BUST_SPINLOCK is not set +# CONFIG_GENERIC_ISA_DMA is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +# CONFIG_OBSOLETE is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y + +# +# System Type +# +# CONFIG_ARCH_ANAKIN is not set +# CONFIG_ARCH_ARCA5K is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CO285 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_CAMELOT is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_OMAHA is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_MX1ADS is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_RISCSTATION is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_SHARK is not set +CONFIG_ARCH_AT91RM9200=y + +# +# Archimedes/A5000 Implementations +# +# CONFIG_ARCH_ARC is not set +# CONFIG_ARCH_A5K is not set + +# +# Footbridge Implementations +# +# CONFIG_ARCH_CATS is not set +# CONFIG_ARCH_PERSONAL_SERVER is not set +# CONFIG_ARCH_EBSA285_ADDIN is not set +# CONFIG_ARCH_EBSA285_HOST is not set +# CONFIG_ARCH_NETWINDER is not set + +# +# SA11x0 Implementations +# +# CONFIG_SA1100_ACCELENT is not set +# CONFIG_SA1100_ASSABET is not set +# CONFIG_ASSABET_NEPONSET is not set +# CONFIG_SA1100_ADSAGC is not set +# CONFIG_SA1100_ADSBITSY is not set +# CONFIG_SA1100_ADSBITSYPLUS is not set +# CONFIG_SA1100_BRUTUS is not set +# CONFIG_SA1100_CEP is not set +# CONFIG_SA1100_CERF is not set +# CONFIG_SA1100_H3100 is not set +# CONFIG_SA1100_H3600 is not set +# CONFIG_SA1100_H3800 is not set +# CONFIG_SA1100_H3XXX is not set +# CONFIG_H3600_SLEEVE is not set +# CONFIG_SA1100_EXTENEX1 is not set +# CONFIG_SA1100_FLEXANET is not set +# CONFIG_SA1100_FREEBIRD is not set +# CONFIG_SA1100_FRODO is not set +# CONFIG_SA1100_GRAPHICSCLIENT is not set +# CONFIG_SA1100_GRAPHICSMASTER is not set +# CONFIG_SA1100_HACKKIT is not set +# CONFIG_SA1100_BADGE4 is not set +# CONFIG_SA1100_JORNADA720 is not set +# CONFIG_SA1100_HUW_WEBPANEL is not set +# CONFIG_SA1100_ITSY is not set +# CONFIG_SA1100_LART is not set +# CONFIG_SA1100_NANOENGINE is not set +# CONFIG_SA1100_OMNIMETER is not set +# CONFIG_SA1100_PANGOLIN is not set +# CONFIG_SA1100_PLEB is not set +# CONFIG_SA1100_PT_SYSTEM3 is not set +# CONFIG_SA1100_SHANNON is not set +# CONFIG_SA1100_SHERMAN is not set +# CONFIG_SA1100_SIMPAD is not set +# CONFIG_SA1100_SIMPUTER is not set +# CONFIG_SA1100_PFS168 is not set +# CONFIG_SA1100_VICTOR is not set +# CONFIG_SA1100_XP860 is not set +# CONFIG_SA1100_YOPY is not set +# CONFIG_SA1100_USB is not set +# CONFIG_SA1100_USB_NETLINK is not set +# CONFIG_SA1100_USB_CHAR is not set +# CONFIG_SA1100_SSP is not set + +# +# AT91RM9200 Implementations +# +# CONFIG_ARCH_AT91RM9200DK is not set +CONFIG_MACH_CSB337=y + +# +# CLPS711X/EP721X Implementations +# +# CONFIG_ARCH_AUTCPU12 is not set +# CONFIG_ARCH_CDB89712 is not set +# CONFIG_ARCH_CLEP7312 is not set +# CONFIG_ARCH_EDB7211 is not set +# CONFIG_ARCH_FORTUNET is not set +# CONFIG_ARCH_GUIDEA07 is not set +# CONFIG_ARCH_P720T is not set +# CONFIG_ARCH_EP7211 is not set +# CONFIG_ARCH_EP7212 is not set +# CONFIG_ARCH_ACORN is not set +# CONFIG_PLD is not set +# CONFIG_FOOTBRIDGE is not set +# CONFIG_FOOTBRIDGE_HOST is not set +# CONFIG_FOOTBRIDGE_ADDIN is not set +CONFIG_CPU_32=y +# CONFIG_CPU_26 is not set +# CONFIG_CPU_ARM610 is not set +# CONFIG_CPU_ARM710 is not set +# CONFIG_CPU_ARM720T is not set +CONFIG_CPU_ARM920T=y +# CONFIG_CPU_ARM922T is not set +# CONFIG_CPU_ARM926T is not set +# CONFIG_CPU_ARM1020 is not set +# CONFIG_CPU_ARM1020E is not set +# CONFIG_CPU_ARM1022 is not set +# CONFIG_CPU_ARM1026 is not set +# CONFIG_CPU_SA110 is not set +# CONFIG_CPU_SA1100 is not set +# CONFIG_CPU_32v3 is not set +CONFIG_CPU_32v4=y +# CONFIG_ARM_THUMB is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_DISCONTIGMEM is not set + +# +# General setup +# +# CONFIG_PCI is not set +# CONFIG_ISA is not set +# CONFIG_ISA_DMA is not set +# CONFIG_ZBOOT_ROM is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +# CONFIG_HOTPLUG is not set +# CONFIG_PCMCIA is not set +CONFIG_NET=y +CONFIG_SYSVIPC=y +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_KCORE_ELF=y +# CONFIG_KCORE_AOUT is not set +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +# CONFIG_PM is not set +# CONFIG_ARTHUR is not set +CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20210000,3145728 root=/dev/ram rw" +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_PARTITIONS is not set +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +# CONFIG_MTD_RAM is not set +CONFIG_MTD_ROM=y +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set +# CONFIG_MTD_AMDSTD is not set +# CONFIG_MTD_SHARP is not set +# CONFIG_MTD_JEDEC is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_START=10000000 +CONFIG_MTD_PHYSMAP_LEN=200000 +CONFIG_MTD_PHYSMAP_BUSWIDTH=2 +# CONFIG_MTD_NORA is not set +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_CDB89712 is not set +# CONFIG_MTD_SA1100 is not set +# CONFIG_MTD_DC21285 is not set +# CONFIG_MTD_IQ80310 is not set +# CONFIG_MTD_FORTUNET is not set +# CONFIG_MTD_EPXA is not set +# CONFIG_MTD_AUTCPU12 is not set +# CONFIG_MTD_EDB7312 is not set +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_CEIVA is not set +# CONFIG_MTD_PCI is not set +# CONFIG_MTD_PCMCIA is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +CONFIG_MTD_AT91_DATAFLASH=y +# CONFIG_MTD_AT91_DATAFLASH_CARD is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLKMTD is not set +# CONFIG_MTD_DOC1000 is not set +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOCPROBE is not set + +# +# NAND Flash Device Drivers +# +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_AT91_SMARTMEDIA is not set + +# +# Plug and Play configuration +# +# CONFIG_PNP is not set +# CONFIG_ISAPNP is not set + +# +# Block devices +# +# CONFIG_BLK_DEV_FD is not set +# CONFIG_BLK_DEV_XD is not set +# CONFIG_PARIDE is not set +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_CISS_SCSI_TAPE is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_BLK_STATS is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set +# CONFIG_BLK_DEV_MD is not set +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_BLK_DEV_LVM is not set + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +# CONFIG_NETLINK_DEV is not set +# CONFIG_NETFILTER is not set +# CONFIG_FILTER is not set +CONFIG_UNIX=y +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_INET_ECN is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_IPV6 is not set +# CONFIG_KHTTPD is not set +# CONFIG_ATM is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set + +# +# Appletalk devices +# +# CONFIG_DEV_APPLETALK is not set +# CONFIG_DECNET is not set +# CONFIG_BRIDGE is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_LLC is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_FASTROUTE is not set +# CONFIG_NET_HW_FLOWCONTROL is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +# CONFIG_ARM_AM79C961A is not set +# CONFIG_ARM_CIRRUS is not set +CONFIG_AT91_ETHER=y +# CONFIG_AT91_ETHER_RMII is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNGEM is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_LANCE is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_NET_ISA is not set +# CONFIG_NET_PCI is not set +# CONFIG_NET_POCKET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set +# CONFIG_NET_FC is not set +# CONFIG_RCPCI is not set +# CONFIG_SHAPER is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set + +# +# Amateur Radio support +# +# CONFIG_HAMRADIO is not set + +# +# IrDA (infrared) support +# +# CONFIG_IRDA is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_HD is not set + +# +# SCSI support +# +# CONFIG_SCSI is not set + +# +# I2O device support +# +# CONFIG_I2O is not set +# CONFIG_I2O_BLOCK is not set +# CONFIG_I2O_LAN is not set +# CONFIG_I2O_SCSI is not set +# CONFIG_I2O_PROC is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Input core support +# +# CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_MX1TS is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL is not set +# CONFIG_SERIAL_EXTENDED is not set +# CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_AT91_SPIDEV=y + +# +# Serial drivers +# +# CONFIG_SERIAL_ANAKIN is not set +# CONFIG_SERIAL_ANAKIN_CONSOLE is not set +# CONFIG_SERIAL_AMBA is not set +# CONFIG_SERIAL_AMBA_CONSOLE is not set +# CONFIG_SERIAL_CLPS711X is not set +# CONFIG_SERIAL_CLPS711X_CONSOLE is not set +# CONFIG_SERIAL_21285 is not set +# CONFIG_SERIAL_21285_OLD is not set +# CONFIG_SERIAL_21285_CONSOLE is not set +# CONFIG_SERIAL_UART00 is not set +# CONFIG_SERIAL_UART00_CONSOLE is not set +# CONFIG_SERIAL_SA1100 is not set +# CONFIG_SERIAL_SA1100_CONSOLE is not set +# CONFIG_SERIAL_OMAHA is not set +# CONFIG_SERIAL_OMAHA_CONSOLE is not set +CONFIG_SERIAL_AT91=y +CONFIG_SERIAL_AT91_CONSOLE=y +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_MANY_PORTS is not set +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_MULTIPORT is not set +# CONFIG_SERIAL_8250_HUB6 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set + +# +# I2C support +# +CONFIG_I2C=y +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +CONFIG_I2C_AT91=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_PROC=y +CONFIG_I2C_DS1307=y + +# +# L3 serial bus support +# +# CONFIG_L3 is not set +# CONFIG_L3_ALGOBIT is not set +# CONFIG_L3_BIT_SA1100_GPIO is not set +# CONFIG_L3_SA1111 is not set +# CONFIG_BIT_SA1100_GPIO is not set + +# +# Mice +# +# CONFIG_BUSMOUSE is not set +# CONFIG_MOUSE is not set + +# +# Joysticks +# +# CONFIG_INPUT_GAMEPORT is not set +# CONFIG_QIC02_TAPE is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMI_PANIC_EVENT is not set +# CONFIG_IPMI_DEVICE_INTERFACE is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_IPMI_WATCHDOG is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_ALIM1535_WDT is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_SC520_WDT is not set +# CONFIG_PCWATCHDOG is not set +# CONFIG_21285_WATCHDOG is not set +# CONFIG_977_WATCHDOG is not set +# CONFIG_SA1100_WATCHDOG is not set +# CONFIG_EPXA_WATCHDOG is not set +# CONFIG_OMAHA_WATCHDOG is not set +CONFIG_AT91_WATCHDOG=y +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_I810_TCO is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_60XX_WDT is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_SCx200_WDT is not set +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_WDT is not set +# CONFIG_WDTPCI is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_AMD7XX_TCO is not set +# CONFIG_SCx200_GPIO is not set +# CONFIG_AMD_PM768 is not set +# CONFIG_NVRAM is not set +# CONFIG_RTC is not set +CONFIG_AT91_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_FTAPE is not set +# CONFIG_AGP is not set +# CONFIG_DRM is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# File systems +# +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_ADFS_FS is not set +# CONFIG_ADFS_FS_RW is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set +# CONFIG_FAT_FS is not set +# CONFIG_MSDOS_FS is not set +# CONFIG_UMSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_TMPFS is not set +CONFIG_RAMFS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_JOLIET is not set +# CONFIG_ZISOFS is not set +# CONFIG_JFS_FS is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_NTFS_FS is not set +# CONFIG_NTFS_RW is not set +# CONFIG_HPFS_FS is not set +CONFIG_PROC_FS=y +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +# CONFIG_DEVPTS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX4FS_RW is not set +# CONFIG_ROMFS_FS is not set +CONFIG_EXT2_FS=y +# CONFIG_SYSV_FS is not set +# CONFIG_UDF_FS is not set +# CONFIG_UDF_RW is not set +# CONFIG_UFS_FS is not set +# CONFIG_UFS_FS_WRITE is not set + +# +# Network File Systems +# +# CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +# CONFIG_NFSD_V3 is not set +# CONFIG_NFSD_TCP is not set +CONFIG_SUNRPC=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +# CONFIG_SMB_FS is not set +# CONFIG_NCP_FS is not set +# CONFIG_NCPFS_PACKET_SIGNING is not set +# CONFIG_NCPFS_IOCTL_LOCKING is not set +# CONFIG_NCPFS_STRONG is not set +# CONFIG_NCPFS_NFS_NS is not set +# CONFIG_NCPFS_OS2_NS is not set +# CONFIG_NCPFS_SMALLDOS is not set +# CONFIG_NCPFS_NLS is not set +# CONFIG_NCPFS_EXTRAS is not set +# CONFIG_ZISOFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_SMB_NLS is not set +# CONFIG_NLS is not set + +# +# Multimedia Capabilities Port drivers +# +# CONFIG_MCP is not set +# CONFIG_MCP_SA1100 is not set +# CONFIG_MCP_UCB1200 is not set +# CONFIG_MCP_UCB1200_AUDIO is not set +# CONFIG_MCP_UCB1200_TS is not set + +# +# USB support +# +# CONFIG_USB is not set + +# +# Bluetooth support +# +# CONFIG_BLUEZ is not set + +# +# Kernel hacking +# +CONFIG_FRAME_POINTER=y +CONFIG_DEBUG_USER=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_NO_PGT_CACHE is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SLAB is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_WAITQ is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_ERRORS is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_DC21285_PORT is not set +# CONFIG_DEBUG_CLPS711X_UART2 is not set + +# +# Library routines +# +# CONFIG_ZLIB_INFLATE is not set +# CONFIG_ZLIB_DEFLATE is not set diff -urN linux-2.4.21-rmk2.orig/arch/arm/mach-at91rm9200/Makefile linux-2.4.21-rmk2/arch/arm/mach-at91rm9200/Makefile --- linux-2.4.21-rmk2.orig/arch/arm/mach-at91rm9200/Makefile Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/arch/arm/mach-at91rm9200/Makefile Mon Mar 8 14:27:28 2004 @@ -18,4 +18,8 @@ export-objs := +# LEDs support +leds-$(CONFIG_ARCH_AT91RM9200DK) += dk-leds.o +obj-$(CONFIG_LEDS) += $(leds-y) + include $(TOPDIR)/Rules.make diff -urN linux-2.4.21-rmk2.orig/arch/arm/mach-at91rm9200/dk-leds.c linux-2.4.21-rmk2/arch/arm/mach-at91rm9200/dk-leds.c --- linux-2.4.21-rmk2.orig/arch/arm/mach-at91rm9200/dk-leds.c Thu Jan 1 02:00:00 1970 +++ linux-2.4.21-rmk2/arch/arm/mach-at91rm9200/dk-leds.c Mon Mar 8 14:27:28 2004 @@ -0,0 +1,97 @@ +/* + * LED driver for the Atmel AT91RM9200 Development Kit. + * + * (c) SAN People (Pty) Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. +*/ + +#include +#include +#include +#include + +#include +#include +#include +#include + + +static inline void at91_led_on(void) +{ + AT91_SYS->PIOB_CODR = AT91C_PIO_PB2; +} + +static inline void at91_led_off(void) +{ + AT91_SYS->PIOB_SODR = AT91C_PIO_PB2; +} + +static inline void at91_led_toggle(void) +{ + unsigned long curr = AT91_SYS->PIOB_ODSR; + if (curr & AT91C_PIO_PB2) + AT91_SYS->PIOB_CODR = AT91C_PIO_PB2; + else + AT91_SYS->PIOB_SODR = AT91C_PIO_PB2; +} + + +/* + * Handle LED events. + */ +static void at91rm9200dk_leds_event(led_event_t evt) +{ + unsigned long flags; + + local_irq_save(flags); + + switch(evt) { + case led_start: /* System startup */ + at91_led_on(); + break; + + case led_stop: /* System stop / suspend */ + at91_led_off(); + break; + +#ifdef CONFIG_LEDS_TIMER + case led_timer: /* Every 50 timer ticks */ + at91_led_toggle(); + break; +#endif + +#ifdef CONFIG_LEDS_CPU + case led_idle_start: /* Entering idle state */ + at91_led_off(); + break; + + case led_idle_end: /* Exit idle state */ + at91_led_on(); + break; +#endif + + default: + break; + } + + local_irq_restore(flags); +} + + +static int __init leds_init(void) +{ + /* Enable PIO to access the LEDs */ + AT91_SYS->PIOB_PER = AT91C_PIO_PB2; + AT91_SYS->PIOB_OER = AT91C_PIO_PB2; + + leds_event = at91rm9200dk_leds_event; + + leds_event(led_start); + return 0; +} + +__initcall(leds_init); diff -urN linux-2.4.21-rmk2.orig/drivers/at91/i2c/at91_i2c.c linux-2.4.21-rmk2/drivers/at91/i2c/at91_i2c.c --- linux-2.4.21-rmk2.orig/drivers/at91/i2c/at91_i2c.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/i2c/at91_i2c.c Mon Mar 8 14:29:52 2004 @@ -46,70 +46,16 @@ static struct at91_i2c_local *at91_i2c_device; /* - * SMBUS-type transfer entrypoint + * Poll the i2c status register until the specified bit is set. + * Returns 0 if timed out (100 msec) */ -static s32 at91_smbus_xfer(struct i2c_adapter *adap, - u16 addr, - unsigned short flags, - char read_write, - u8 command, int size, union i2c_smbus_data *data) -{ -#if 0 - struct at91_i2c_local *device = (struct at91_i2c_local *) adap->data; - int len; - u8 *buffer; - u16 cur_word; - int rc = 0; - - /* Prepare datas & select mode */ - switch (size) { - case I2C_SMBUS_QUICK: - len = 0; - buffer = NULL; - break; - case I2C_SMBUS_BYTE: - len = 1; - buffer = &data->byte; - break; - case I2C_SMBUS_BYTE_DATA: - len = 1; - buffer = &data->byte; - break; - case I2C_SMBUS_WORD_DATA: - len = 2; - cur_word = cpu_to_le16(data->word); - buffer = (u8 *) & cur_word; - break; - case I2C_SMBUS_BLOCK_DATA: - len = data->block[0]; - buffer = &data->block[1]; - break; - default: - return -1; - } - - /* Original driver had this limitation */ - if (len > 32) - len = 32; - - DBG("chan: %d, addr: 0x%x, transfer len: %d, read: %d\n", - device->chan_no, addr, len, read_write == I2C_SMBUS_READ); - - /* Set up address and r/w bit */ - write_reg(reg_addr, (addr << 1) | ((read_write == I2C_SMBUS_READ) ? 0x01 : 0x00)); - - /* Set up the sub address */ +static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) { + int loop_cntr = 10000; + do { + udelay(10); + } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0)); - /* Start sending address & enable interrupt */ - write_reg(reg_control, read_reg(reg_control) | KW_I2C_CTL_XADDR); - write_reg(reg_ier, KW_I2C_IRQ_MASK); - - DBG("transfer done\n"); - - if (size == I2C_SMBUS_WORD_DATA && read_write == I2C_SMBUS_READ) - data->word = le16_to_cpu(cur_word); -#endif - return 0; + return (loop_cntr > 0); } /* @@ -121,11 +67,17 @@ AT91PS_TWI twi = (AT91PS_TWI) device->base_addr; struct i2c_msg *pmsg; - int completed = 0, length; + int length; unsigned char *buf; + /* + * i2c_smbus_xfer_emulated() in drivers/i2c/i2c-core.c states: + * "... In the case of writing, we need to use only one message; + * when reading, we need two..." + */ + pmsg = msgs; /* look at 1st message, it contains the address/command */ - if (num == 2 && pmsg->len >= 1 && pmsg->len <= 3) { + if (num >= 1 && num <= 2) { DBG("xfer: doing %s %d bytes to 0x%02x - %d messages\n", pmsg->flags & I2C_M_RD ? "read" : "write", pmsg->len, pmsg->buf[0], num); @@ -142,7 +94,10 @@ else /* must be 3 */ twi->TWI_IADR = pmsg->buf[0] << 16 | pmsg->buf[1] << 8 | pmsg->buf[2]; - pmsg++; /* go to real message */ + /* 1st message contains the address/command */ + if (num > 1) + pmsg++; /* go to real message */ + length = pmsg->len; buf = pmsg->buf; if (length && buf) { /* sanity check */ @@ -152,33 +107,41 @@ if (!length) twi->TWI_CR = AT91C_TWI_STOP; /* Wait until transfer is finished */ - do - udelay(10); - while (!(twi->TWI_SR & AT91C_TWI_RXRDY)); + if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) { + printk(KERN_ERR "at91_i2c: timeout 1\n"); + return 0; + } *buf++ = twi->TWI_RHR; } - do { - udelay(10); - } while (!(twi->TWI_SR & AT91C_TWI_TXCOMP)); + if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { + printk(KERN_ERR "at91_i2c: timeout 2\n"); + return 0; + } } else { twi->TWI_CR = AT91C_TWI_START; while (length--) { twi->TWI_THR = *buf++; if (!length) twi->TWI_CR = AT91C_TWI_STOP; - do { - udelay(10); - } while (!(twi->TWI_SR & AT91C_TWI_TXRDY)); + if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) { + printk(KERN_ERR "at91_i2c: timeout 3\n"); + return 0; + } } /* Wait until transfer is finished */ - do { - udelay(10); - } while (!(twi->TWI_SR & AT91C_TWI_TXCOMP)); + if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) { + printk(KERN_ERR "at91_i2c: timeout 4\n"); + return 0; + } } } + DBG("transfer complete\n"); + return num; + } + else { + printk(KERN_ERR "at91_i2c: unexpected number of messages: %d\n", num); + return 0; } - DBG("transfer done\n"); - return completed++; } /* @@ -197,7 +160,6 @@ static void at91_inc(struct i2c_adapter *adapter) { MOD_INC_USE_COUNT; - AT91_SYS->PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ } /* @@ -205,7 +167,6 @@ */ static void at91_dec(struct i2c_adapter *adapter) { - AT91_SYS->PMC_PCDR = 1 << AT91C_ID_TWI; /* disable peripheral clock */ MOD_DEC_USE_COUNT; } @@ -213,7 +174,6 @@ static struct i2c_algorithm at91_algorithm = { name:"at91 i2c", id:I2C_ALGO_SMBUS, - smbus_xfer:at91_smbus_xfer, master_xfer:at91_xfer, functionality:at91_func, }; @@ -228,6 +188,7 @@ int rc; AT91_CfgPIO_TWI(); + AT91_SYS->PMC_PCER = 1 << AT91C_ID_TWI; /* enable peripheral clock */ twi->TWI_IDR = 0x3ff; /* Disable all interrupts */ twi->TWI_CR = AT91C_TWI_SWRST; /* Reset peripheral */ @@ -277,6 +238,8 @@ rc = i2c_del_adapter(&device->adapter); device->adapter.data = NULL; kfree(device); + + AT91_SYS->PMC_PCDR = 1 << AT91C_ID_TWI; /* disable peripheral clock */ /* We aren't that prepared to deal with this... */ if (rc) diff -urN linux-2.4.21-rmk2.orig/drivers/at91/i2c/at91_i2c.h linux-2.4.21-rmk2/drivers/at91/i2c/at91_i2c.h --- linux-2.4.21-rmk2.orig/drivers/at91/i2c/at91_i2c.h Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/i2c/at91_i2c.h Mon Mar 8 14:29:56 2004 @@ -23,7 +23,7 @@ #define AT91C_TWI_CLOCK 100000 #define AT91C_TWI_SCLOCK (10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK) -#define AT91C_TWI_CKDIV1 (1 << 16) /* TWI clock divider */ +#define AT91C_TWI_CKDIV1 (2 << 16) /* TWI clock divider. NOTE: see Errata #22 */ #if (AT91C_TWI_SCLOCK % 10) >= 5 #define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5) diff -urN linux-2.4.21-rmk2.orig/drivers/at91/mtd/at91_dataflash.c linux-2.4.21-rmk2/drivers/at91/mtd/at91_dataflash.c --- linux-2.4.21-rmk2.orig/drivers/at91/mtd/at91_dataflash.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/mtd/at91_dataflash.c Mon Mar 8 14:27:28 2004 @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -68,12 +69,12 @@ If this is not valid, then either (i) each dataflash 'priv' structure needs it's own transfer descriptor, (ii) we lock this one, or (iii) use another mechanism. */ -struct spi_transfer_list* spi_transfer_desc; +static struct spi_transfer_list* spi_transfer_desc; /* * Perform a SPI transfer to access the DataFlash device. */ -int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len, +static int do_spi_transfer(int nr, char* tx, int tx_len, char* rx, int rx_len, char* txnext, int txnext_len, char* rxnext, int rxnext_len) { struct spi_transfer_list* list = spi_transfer_desc; @@ -94,7 +95,7 @@ /* * Poll the DataFlash device until it is READY. */ -void at91_dataflash_waitready(void) +static void at91_dataflash_waitready(void) { char* command = kmalloc(2, GFP_KERNEL); @@ -114,7 +115,7 @@ /* * Return the status of the DataFlash device. */ -unsigned short at91_dataflash_status(void) +static unsigned short at91_dataflash_status(void) { unsigned short status; char* command = kmalloc(2, GFP_KERNEL); @@ -135,9 +136,9 @@ /* ......................................................................... */ /* - * Erase a block of flash. + * Erase blocks of flash. */ -int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) +static int at91_dataflash_erase(struct mtd_info *mtd, struct erase_info *instr) { struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; unsigned int pageaddr; @@ -150,7 +151,7 @@ /* Sanity checks */ if (instr->addr + instr->len > mtd->size) return -EINVAL; - if ((instr->len != mtd->erasesize) || (instr->len != priv->page_size)) + if ((instr->len % mtd->erasesize != 0) || (instr->len % priv->page_size != 0)) return -EINVAL; if ((instr->addr % priv->page_size) != 0) return -EINVAL; @@ -159,23 +160,28 @@ if (!command) return -ENOMEM; - /* Calculate flash page address */ - pageaddr = (instr->addr / priv->page_size) << priv->page_offset; - - command[0] = OP_ERASE_PAGE; - command[1] = (pageaddr & 0x00FF0000) >> 16; - command[2] = (pageaddr & 0x0000FF00) >> 8; - command[3] = 0; + while (instr->len > 0) { + /* Calculate flash page address */ + pageaddr = (instr->addr / priv->page_size) << priv->page_offset; + + command[0] = OP_ERASE_PAGE; + command[1] = (pageaddr & 0x00FF0000) >> 16; + command[2] = (pageaddr & 0x0000FF00) >> 8; + command[3] = 0; #ifdef DEBUG_DATAFLASH - printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr); + printk("ERASE: (%x) %x %x %x [%i]\n", command[0], command[1], command[2], command[3], pageaddr); #endif - /* Send command to SPI device */ - spi_access_bus(priv->spi); - do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0); + /* Send command to SPI device */ + spi_access_bus(priv->spi); + do_spi_transfer(1, command, 4, command, 4, NULL, 0, NULL, 0); - at91_dataflash_waitready(); /* poll status until ready */ - spi_release_bus(priv->spi); + at91_dataflash_waitready(); /* poll status until ready */ + spi_release_bus(priv->spi); + + instr->addr += priv->page_size; /* next page */ + instr->len -= priv->page_size; + } kfree(command); @@ -194,7 +200,7 @@ * retlen : About of data actually read * buf : Buffer containing the data */ -int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) +static int at91_dataflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; unsigned int addr; @@ -244,15 +250,16 @@ * retlen : Amount of data actually written * buf : Buffer containing the data */ -int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) +static int at91_dataflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) { struct dataflash_local *priv = (struct dataflash_local *) mtd->priv; unsigned int pageaddr, addr, offset, writelen; size_t remaining; - char *writebuf; + u_char *writebuf; unsigned short status; int res = 0; char* command; + char* tmpbuf = NULL; #ifdef DEBUG_DATAFLASH printk("dataflash_write: %lli .. %lli\n", to, to+len); @@ -279,6 +286,13 @@ writebuf = buf; remaining = len; + /* Allocate temporary buffer */ + tmpbuf = kmalloc(priv->page_size, GFP_KERNEL); + if (!tmpbuf) { + kfree(command); + return -ENOMEM; + } + /* Gain access to the SPI bus */ spi_access_bus(priv->spi); @@ -310,7 +324,7 @@ #ifdef DEBUG_DATAFLASH printk("PROGRAM: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); #endif - do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, writebuf, writelen); + do_spi_transfer(2, command, 4, command, 4, writebuf, writelen, tmpbuf, writelen); at91_dataflash_waitready(); /* (3) Compare to Buffer1 */ @@ -348,6 +362,7 @@ /* Release SPI bus */ spi_release_bus(priv->spi); + kfree(tmpbuf); kfree(command); return res; } @@ -357,7 +372,7 @@ /* * Initialize and register DataFlash device with MTD subsystem. */ -int add_dataflash(int channel, char *name, int size, int pagesize, int pageoffset) +static int add_dataflash(int channel, char *name, int IDsize, int nr_pages, int pagesize, int pageoffset) { struct mtd_info *device; struct dataflash_local *priv; @@ -376,7 +391,7 @@ memset(device, 0, sizeof(struct mtd_info)); device->name = name; - device->size = size; + device->size = nr_pages * pagesize; device->erasesize = pagesize; device->module = THIS_MODULE; device->type = MTD_NORFLASH; @@ -399,7 +414,7 @@ mtd_devices[nr_devices] = device; nr_devices++; - printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, size); + printk("at91_dataflash: %s detected [spi%i] (%i bytes)\n", name, channel, device->size); #ifdef CONFIG_MTD_PARTITIONS #ifdef CONFIG_MTD_CMDLINE_PARTS @@ -411,16 +426,30 @@ mtd_parts_nr = NB_OF(static_partitions); } - return add_mtd_partitions(device, mtd_parts, mtd_parts_nr); -#else - return add_mtd_device(device); + if (mtd_parts_nr > 0) { +#ifdef DATAFLASH_ALWAYS_ADD_DEVICE + add_mtd_device(device); +#endif + return add_mtd_partitions(device, mtd_parts, mtd_parts_nr); + } #endif + return add_mtd_device(device); /* add whole device */ } /* * Detect and initialize DataFlash device connected to specified SPI channel. + * + * Device Density ID code Nr Pages Page Size Page offset + * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9 + * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1025 264 9 + * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9 + * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9 + * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10 + * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10 + * AT45DB0642 64Mbit (8M) xx1111xx (0x3c) 8192 1056 11 + * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11 */ -int at91_dataflash_detect(int channel) +static int at91_dataflash_detect(int channel) { int res = 0; unsigned short status; @@ -429,15 +458,31 @@ status = at91_dataflash_status(); if (status != 0xff) { /* no dataflash device there */ switch (status & 0x3c) { + case 0x0c: /* 0 0 1 1 */ + res = add_dataflash(channel, "Atmel AT45DB011B", SZ_128K, 512, 264, 9); + break; + case 0x14: /* 0 1 0 1 */ + res = add_dataflash(channel, "Atmel AT45DB021B", SZ_256K, 1025, 264, 9); + break; + case 0x1c: /* 0 1 1 1 */ + res = add_dataflash(channel, "Atmel AT45DB041B", SZ_512K, 2048, 264, 9); + break; + case 0x24: /* 1 0 0 1 */ + res = add_dataflash(channel, "Atmel AT45DB081B", SZ_1M, 4096, 264, 9); + break; case 0x2c: /* 1 0 1 1 */ - res = add_dataflash(channel, "Atmel AT45DB161B", 4096*528, 528, 10); + res = add_dataflash(channel, "Atmel AT45DB161B", SZ_2M, 4096, 528, 10); break; case 0x34: /* 1 1 0 1 */ - res = add_dataflash(channel, "Atmel AT45DB321B", 8192*528, 528, 10); + res = add_dataflash(channel, "Atmel AT45DB321B", SZ_4M, 8192, 528, 10); break; case 0x3c: /* 1 1 1 1 */ - res = add_dataflash(channel, "Atmel AT45DB642", 8192*1056, 1056, 11); + res = add_dataflash(channel, "Atmel AT45DB642", SZ_8M, 8192, 1056, 11); break; +// Currently unsupported since Atmel removed the "Main Memory Program via Buffer" commands. +// case 0x10: /* 0 1 0 0 */ +// res = add_dataflash(channel, "Atmel AT45DB1282", SZ_16M, 16384, 1056, 11); +// break; default: printk(KERN_ERR "at91_dataflash: Unknown device (%x)\n", status & 0x3c); } @@ -447,7 +492,7 @@ return res; } -int __init at91_dataflash_init(void) +static int __init at91_dataflash_init(void) { spi_transfer_desc = kmalloc(sizeof(struct spi_transfer_list), GFP_KERNEL); if (!spi_transfer_desc) @@ -465,7 +510,7 @@ return 0; } -void __exit at91_dataflash_exit(void) +static void __exit at91_dataflash_exit(void) { int i; diff -urN linux-2.4.21-rmk2.orig/drivers/at91/mtd/at91_dataflash.h linux-2.4.21-rmk2/drivers/at91/mtd/at91_dataflash.h --- linux-2.4.21-rmk2.orig/drivers/at91/mtd/at91_dataflash.h Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/mtd/at91_dataflash.h Mon Mar 8 14:27:28 2004 @@ -13,6 +13,7 @@ #define AT91_DATAFLASH_H #define DATAFLASH_MAX_DEVICES 4 /* max number of dataflash devices */ +#undef DATAFLASH_ALWAYS_ADD_DEVICE /* always add whole device when using partitions? */ #define OP_READ_CONTINUOUS 0xE8 #define OP_READ_PAGE 0xD2 diff -urN linux-2.4.21-rmk2.orig/drivers/at91/mtd/at91_nand.c linux-2.4.21-rmk2/drivers/at91/mtd/at91_nand.c --- linux-2.4.21-rmk2.orig/drivers/at91/mtd/at91_nand.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/mtd/at91_nand.c Mon Mar 8 14:27:28 2004 @@ -31,7 +31,7 @@ * MTD structure for AT91 board */ static struct mtd_info *at91_mtd = NULL; -static struct nand_chip *my_nand_chip; +static struct nand_chip *my_nand_chip = NULL; static int at91_fio_base; @@ -79,7 +79,7 @@ /* * Hardware specific access to control-lines */ -void at91_hwcontrol(int cmd) +static void at91_hwcontrol(int cmd) { struct nand_chip *my_nand = my_nand_chip; switch(cmd) @@ -168,14 +168,14 @@ /* * Read the Device Ready pin. */ -int at91_device_ready(void) +static int at91_device_ready(void) { return AT91_PIO_SmartMedia_RDY(); } /* * Main initialization routine */ -int __init at91_init (void) +static int __init at91_init (void) { struct nand_chip *my_nand; int err = 0; @@ -211,7 +211,8 @@ my_nand->IO_ADDR_W = at91_fio_base; my_nand->hwcontrol = at91_hwcontrol; my_nand->dev_ready = at91_device_ready; - my_nand->cmdfunc = at91_nand_command; /* we need our own */ + my_nand->eccmode = NAND_ECC_SOFT; /* enable ECC */ + my_nand->cmdfunc = at91_nand_command; /* we need our own */ /* 20 us command delay time */ my_nand->chip_delay = 20; @@ -222,11 +223,11 @@ tDH Data Hold Time 20 - ns tALS ALE Set up Time 20 - ns 16ns at 60 MHz ~= 3 */ -#define AT91C_SM_ID_RWH (5 << 28) /* debug only orig = 5 */ +#define AT91C_SM_ID_RWH (5 << 28) /* orig = 5 */ #define AT91C_SM_RWH (1 << 28) /* orig = 1 */ #define AT91C_SM_RWS (0 << 24) /* orig = 0 */ #define AT91C_SM_TDF (1 << 8) /* orig = 1 */ -#define AT91C_SM_NWS (3) /* orig = 3 */ +#define AT91C_SM_NWS (5) /* orig = 3 */ AT91_SYS->EBI_SMC2_CSR[3] = ( AT91C_SM_RWH | AT91C_SM_RWS | AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 | AT91C_SM_TDF | diff -urN linux-2.4.21-rmk2.orig/drivers/at91/net/at91_ether.c linux-2.4.21-rmk2/drivers/at91/net/at91_ether.c --- linux-2.4.21-rmk2.orig/drivers/at91/net/at91_ether.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/net/at91_ether.c Mon Mar 8 14:27:28 2004 @@ -6,6 +6,9 @@ * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc. * Initial version by Rick Bronson 01/11/2003 * + * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker + * (Polaroid Corporation) + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version @@ -55,10 +58,10 @@ * Write value to the a PHY register * Note: MDI interface is assumed to already have been enabled. */ -static void write_phy(AT91PS_EMAC regs, unsigned char address, unsigned int value) +static void write_phy(AT91PS_EMAC regs, unsigned char phy_addr, unsigned char address, unsigned int value) { regs->EMAC_MAN = (AT91C_EMAC_HIGH | AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W - | (address << 18)) + (value & 0xffff); + | ((phy_addr & 0x1f) << 23) | (address << 18)) + (value & 0xffff); /* Wait until IDLE bit in Network Status register is cleared */ // TODO: Enforce some maximum loop-count? @@ -69,10 +72,10 @@ * Read value stored in a PHY register. * Note: MDI interface is assumed to already have been enabled. */ -static void read_phy(AT91PS_EMAC regs, unsigned char address, unsigned int *value) +static void read_phy(AT91PS_EMAC regs, unsigned char phy_addr, unsigned char address, unsigned int *value) { regs->EMAC_MAN = AT91C_EMAC_HIGH | AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_R - | (address << 18); + | ((phy_addr & 0x1f) << 23) | (address << 18); /* Wait until IDLE bit in Network Status register is cleared */ // TODO: Enforce some maximum loop-count? @@ -96,15 +99,15 @@ unsigned int speed, duplex; /* Link status is latched, so read twice to get current value */ - read_phy(regs, MII_BMSR, &bmsr); - read_phy(regs, MII_BMSR, &bmsr); + read_phy(regs, 0, MII_BMSR, &bmsr); + read_phy(regs, 0, MII_BMSR, &bmsr); if (!(bmsr & BMSR_LSTATUS)) return -1; /* no link */ - read_phy(regs, MII_BMCR, &bmcr); + read_phy(regs, 0, MII_BMCR, &bmcr); if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */ if (!(bmsr & BMSR_ANEGCOMPLETE)) return -2; /* auto-negotitation in progress */ - read_phy(regs, MII_LPA, &lpa); + read_phy(regs, 0, MII_LPA, &lpa); if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100; else speed = SPEED_10; if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL; @@ -135,16 +138,20 @@ /* * Handle interrupts from the PHY */ -void at91ether_phy_interrupt(int irq, void *dev_id, struct pt_regs *regs) +static void at91ether_phy_interrupt(int irq, void *dev_id, struct pt_regs *regs) { struct net_device *dev = (struct net_device *) dev_id; + struct at91_private *lp = (struct at91_private *) dev->priv; AT91PS_EMAC emac = (AT91PS_EMAC) dev->base_addr; int status; unsigned int phy; enable_mdi(emac); - - read_phy(emac, MII_DSINTR_REG, &phy); /* acknowledge interrupt in PHY */ + if (lp->phy_type == MII_DM9161_ID) + read_phy(emac, 0, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */ + else if (lp->phy_type == MII_LXT971A_ID) + read_phy(emac, 0, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */ + status = AT91_SYS->PIOC_ISR; /* acknowledge interrupt in PIO */ status = update_linkspeed(dev, emac); @@ -162,61 +169,103 @@ /* * Initialize and enable the PHY interrupt when link-state changes */ -void enable_phyirq(struct net_device *dev, AT91PS_EMAC regs) +static void enable_phyirq(struct net_device *dev, AT91PS_EMAC regs) { struct at91_private *lp = (struct at91_private *) dev->priv; unsigned int dsintr, status; - static int first_init = 0; - - if (first_init == 0) { - // TODO: Check error code. Really need a generic PIO (interrupt) - // layer since we're really only interested in the PC4 line. - (void) request_irq(4, at91ether_phy_interrupt, 0, dev->name, dev); - - AT91_SYS->PIOC_ODR = AT91C_PIO_PC4; /* Configure as input */ - - first_init = 1; - } - else { - status = AT91_SYS->PIOC_ISR; /* clear any pending PIO interrupts */ - AT91_SYS->PIOC_IER = AT91C_PIO_PC4; /* Enable interrupt */ + // TODO: Check error code. Really need a generic PIO (interrupt) + // layer since we're really only interested in the PC4 (DK) or PC2 (CSB337) line. + (void) request_irq(AT91C_ID_PIOC, at91ether_phy_interrupt, 0, dev->name, dev); + + status = AT91_SYS->PIOC_ISR; /* clear any pending PIO interrupts */ +#ifdef CONFIG_MACH_CSB337 + AT91_SYS->PIOC_IER = AT91C_PIO_PC2; /* Enable interrupt */ +#else + AT91_SYS->PIOC_IER = AT91C_PIO_PC4; /* Enable interrupt */ +#endif - spin_lock_irq(&lp->lock); - enable_mdi(regs); - read_phy(regs, MII_DSINTR_REG, &dsintr); + spin_lock_irq(&lp->lock); + enable_mdi(regs); + + if (lp->phy_type == MII_DM9161_ID) { /* for Davicom PHY */ + read_phy(regs, 0, MII_DSINTR_REG, &dsintr); dsintr = dsintr & ~0xf00; /* clear bits 8..11 */ - write_phy(regs, MII_DSINTR_REG, dsintr); - disable_mdi(regs); - spin_unlock_irq(&lp->lock); + write_phy(regs, 0, MII_DSINTR_REG, dsintr); + } + else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ + read_phy(regs, 0, MII_ISINTE_REG, &dsintr); + dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */ + write_phy(regs, 0, MII_ISINTE_REG, dsintr); } + + disable_mdi(regs); + spin_unlock_irq(&lp->lock); } /* * Disable the PHY interrupt */ -void disable_phyirq(struct net_device *dev, AT91PS_EMAC regs) +static void disable_phyirq(struct net_device *dev, AT91PS_EMAC regs) { struct at91_private *lp = (struct at91_private *) dev->priv; unsigned int dsintr; spin_lock_irq(&lp->lock); enable_mdi(regs); - read_phy(regs, MII_DSINTR_REG, &dsintr); - dsintr = dsintr | 0xf00; /* set bits 8..11 */ - write_phy(regs, MII_DSINTR_REG, dsintr); + + if (lp->phy_type == MII_DM9161_ID) { /* for Davicom PHY */ + read_phy(regs, 0, MII_DSINTR_REG, &dsintr); + dsintr = dsintr | 0xf00; /* set bits 8..11 */ + write_phy(regs, 0, MII_DSINTR_REG, dsintr); + } + else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */ + read_phy(regs, 0, MII_ISINTE_REG, &dsintr); + dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */ + write_phy(regs, 0, MII_ISINTE_REG, dsintr); + } + disable_mdi(regs); spin_unlock_irq(&lp->lock); +#ifdef CONFIG_MACH_CSB337 + AT91_SYS->PIOC_IDR = AT91C_PIO_PC2; /* Disable interrupt */ +#else AT91_SYS->PIOC_IDR = AT91C_PIO_PC4; /* Disable interrupt */ +#endif + free_irq(AT91C_ID_PIOC, dev); /* Free interrupt handler */ +} + +/* + * Perform a software reset of the PHY. + */ +static void reset_phy(struct net_device *dev, AT91PS_EMAC regs) +{ + struct at91_private *lp = (struct at91_private *) dev->priv; + unsigned int bmcr; + + spin_lock_irq(&lp->lock); + enable_mdi(regs); + + /* Perform PHY reset */ + write_phy(regs, 0, MII_BMCR, BMCR_RESET); + + /* Wait until PHY reset is complete */ + do { + read_phy(regs, 0, MII_BMCR, &bmcr); + } while (!(bmcr && BMCR_RESET)); + + disable_mdi(regs); + spin_unlock_irq(&lp->lock); } + /* ......................... ADDRESS MANAGEMENT ........................ */ /* * Set the ethernet MAC address in dev->dev_addr */ -void get_mac_address(struct net_device *dev) { +static void get_mac_address(struct net_device *dev) { AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr; char addr[6]; unsigned int hi, lo; @@ -342,7 +391,7 @@ AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr; unsigned int value; - read_phy(regs, location, &value); + read_phy(regs, phy_id, location, &value); return value; } @@ -350,7 +399,7 @@ { AT91PS_EMAC regs = (AT91PS_EMAC) dev->base_addr; - write_phy(regs, location, value); + write_phy(regs, phy_id, location, value); } /* @@ -373,6 +422,10 @@ case ETHTOOL_GSET: { struct ethtool_cmd ecmd = { ETHTOOL_GSET }; res = mii_ethtool_gset(&lp->mii, &ecmd); + if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */ + ecmd.supported = SUPPORTED_FIBRE; + ecmd.port = PORT_FIBRE; + } if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) res = -EFAULT; break; @@ -464,7 +517,7 @@ return -EADDRNOTAVAIL; AT91_SYS->PMC_PCER = 1 << AT91C_ID_EMAC; /* Re-enable Peripheral clock */ - regs->EMAC_CTL |= AT91C_EMAC_CSR; /* Clear internal statistics */ + regs->EMAC_CTL |= AT91C_EMAC_CSR; /* Clear internal statistics */ /* Enable PHY interrupt */ enable_phyirq(dev, regs); @@ -659,11 +712,12 @@ /* * Initialize the ethernet interface */ -static int at91ether_setup(struct net_device *dev) +static int at91ether_setup(struct net_device *dev, unsigned long phy_type) { struct at91_private *lp; AT91PS_EMAC regs; static int already_initialized = 0; + unsigned int val; if (already_initialized) return 0; @@ -715,16 +769,30 @@ regs->EMAC_CTL = 0; #ifdef CONFIG_AT91_ETHER_RMII - regs->EMAC_CFG = AT91C_EMAC_RMII; + regs->EMAC_CFG = AT91C_EMAC_BIG | AT91C_EMAC_RMII; #else - regs->EMAC_CFG = 0; + regs->EMAC_CFG = AT91C_EMAC_BIG; #endif + if (phy_type == MII_LXT971A_ID) + regs->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64; /* MDIO clock = system clock/64 */ + + if (phy_type == MII_DM9161_ID) { + spin_lock_irq(&lp->lock); + enable_mdi(regs); + + read_phy(regs, 0, MII_DSCR_REG, &val); + if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */ + lp->phy_media = PORT_FIBRE; + + disable_mdi(regs); + spin_unlock_irq(&lp->lock); + } lp->mii.dev = dev; /* Support for ethtool */ lp->mii.mdio_read = mdio_read; lp->mii.mdio_write = mdio_write; - - enable_phyirq(dev, regs); + + lp->phy_type = phy_type; /* Type of PHY connected */ /* Determine current link speed */ spin_lock_irq(&lp->lock); @@ -740,6 +808,10 @@ regs->EMAC_CFG & AT91C_EMAC_FD ? "FullDuplex" : "HalfDuplex", dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); + if (phy_type == MII_DM9161_ID) + printk(KERN_INFO "%s: Davicom 9196 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)"); + else if (phy_type == MII_LXT971A_ID) + printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name); already_initialized = 1; return 0; @@ -748,7 +820,7 @@ /* * Detect MAC and PHY and perform initialization */ -int at91ether_probe(struct net_device *dev) +static int at91ether_probe(struct net_device *dev) { AT91PS_EMAC regs = (AT91PS_EMAC) AT91C_VA_BASE_EMAC; unsigned int phyid1, phyid2; @@ -761,17 +833,22 @@ AT91_CfgPIO_EMAC_MII(); #endif + AT91_CfgPIO_EMAC_PHY(); /* Configure PHY interrupt */ AT91_SYS->PMC_PCER = 1 << AT91C_ID_EMAC; /* Enable Peripheral clock */ /* Read the PHY ID registers */ enable_mdi(regs); - read_phy(regs, MII_PHYSID1, &phyid1); - read_phy(regs, MII_PHYSID2, &phyid2); + read_phy(regs, 0, MII_PHYSID1, &phyid1); + read_phy(regs, 0, MII_PHYSID2, &phyid2); disable_mdi(regs); /* Davicom 9161: PHY_ID1 = 0x181 PHY_ID2 = B881 */ if (((phyid1 << 16) | (phyid2 & 0xfff0)) == MII_DM9161_ID) { - detected = at91ether_setup(dev); + detected = at91ether_setup(dev, MII_DM9161_ID); + } + /* Intel LXT971A: PHY_ID1 = 0x13 PHY_ID2 = 78E0 */ + else if (((phyid1 << 16) | (phyid2 & 0xfff0)) == MII_LXT971A_ID) { + detected = at91ether_setup(dev, MII_LXT971A_ID); } AT91_SYS->PMC_PCDR = 1 << AT91C_ID_EMAC; /* Disable Peripheral clock */ diff -urN linux-2.4.21-rmk2.orig/drivers/at91/net/at91_ether.h linux-2.4.21-rmk2/drivers/at91/net/at91_ether.h --- linux-2.4.21-rmk2.orig/drivers/at91/net/at91_ether.h Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/net/at91_ether.h Mon Mar 8 14:27:28 2004 @@ -22,9 +22,17 @@ #define MII_DM9161_ID 0x0181b880 /* Davicom specific registers */ +#define MII_DSCR_REG 16 #define MII_DSCSR_REG 17 #define MII_DSINTR_REG 21 +/* Intel LXT971A PHY */ +#define MII_LXT971A_ID 0x001378E0 + +/* Intel specific registers */ +#define MII_ISINTE_REG 18 +#define MII_ISINTS_REG 19 + /* ........................................................................ */ #define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */ @@ -55,7 +63,9 @@ struct mii_if_info mii; /* ethtool support */ /* PHY */ + unsigned long phy_type; /* type of PHY (PHY_ID) */ spinlock_t lock; /* lock for MDI interface */ + short phy_media; /* media interface type */ /* Transmit */ struct sk_buff *skb; /* holds skb until xmit interrupt completes */ diff -urN linux-2.4.21-rmk2.orig/drivers/at91/rtc/at91_rtc.c linux-2.4.21-rmk2/drivers/at91/rtc/at91_rtc.c --- linux-2.4.21-rmk2.orig/drivers/at91/rtc/at91_rtc.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/rtc/at91_rtc.c Mon Mar 8 14:27:28 2004 @@ -94,7 +94,7 @@ | BIN2BCD(tval->tm_min) << 8 | BIN2BCD(tval->tm_hour) << 16; - AT91_SYS->RTC_CALR = BIN2BCD(tval->tm_year / 100) /* century */ + AT91_SYS->RTC_CALR = BIN2BCD((tval->tm_year + 1900) / 100) /* century */ | BIN2BCD(tval->tm_year % 100) << 8 /* year */ | BIN2BCD(tval->tm_mon + 1) << 16 /* tm_mon starts at zero */ | BIN2BCD(tval->tm_wday + 1) << 21 /* day of the week [0-6], Sunday=0 */ @@ -180,7 +180,7 @@ return (rtc_irq_data) ? 0 : POLLIN | POLLRDNORM; } -ssize_t at91_rtc_read(struct file * file, char *buf, size_t count, loff_t * ppos) +static ssize_t at91_rtc_read(struct file * file, char *buf, size_t count, loff_t * ppos) { DECLARE_WAITQUEUE(wait, current); unsigned long data; @@ -222,7 +222,7 @@ out: set_current_state(TASK_RUNNING); remove_wait_queue(&at91_rtc_wait, &wait); - remove_wait_queue(&at91_rtc_update, &wait); +// remove_wait_queue(&at91_rtc_update, &wait); return retval; } @@ -262,6 +262,7 @@ rtc_irq_data = 0; break; case RTC_ALM_READ: /* read alarm */ + memset(&tm, 0, sizeof(struct rtc_time)); at91_rtc_decodetime(&(AT91_SYS->RTC_TIMALR), &(AT91_SYS->RTC_CALALR), &tm); tm.tm_yday = compute_yday(tm.tm_year, tm.tm_mon, tm.tm_mday); tm.tm_year = at91_alarm_year - 1900; @@ -290,6 +291,7 @@ } break; case RTC_RD_TIME: /* read time */ + memset(&tm, 0, sizeof(struct rtc_time)); at91_rtc_decodetime(&(AT91_SYS->RTC_TIMR), &(AT91_SYS->RTC_CALR), &tm); tm.tm_yday = compute_yday(tm.tm_year, tm.tm_mon, tm.tm_mday); tm.tm_year = tm.tm_year - 1900; diff -urN linux-2.4.21-rmk2.orig/drivers/at91/serial/at91_serial.c linux-2.4.21-rmk2/drivers/at91/serial/at91_serial.c --- linux-2.4.21-rmk2.orig/drivers/at91/serial/at91_serial.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/serial/at91_serial.c Mon Mar 8 14:27:28 2004 @@ -32,32 +32,16 @@ #include #include #include +#include #include +#include #include -/* - * This is a temporary structure for registering these - * functions; it is intended to be discarded after boot. - */ -struct uart_port; -struct uart_info; -struct at91_port_fns { - void (*set_mctrl)(struct uart_port *, u_int); - u_int (*get_mctrl)(struct uart_port *); - void (*enable_ms)(struct uart_port *); - void (*pm)(struct uart_port *, u_int, u_int); - int (*set_wake)(struct uart_port *, u_int); - int (*open)(struct uart_port *, struct uart_info *); - void (*close)(struct uart_port *, struct uart_info *); -}; - #if defined(CONFIG_SERIAL_AT91_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) #define SUPPORT_SYSRQ #endif -#include - #define SERIAL_AT91_MAJOR TTY_MAJOR #define CALLOUT_AT91_MAJOR TTYAUX_MAJOR #define MINOR_START 64 @@ -76,14 +60,34 @@ #define UART_PUT_CHAR(port,v) ((AT91PS_USART)(port)->membase)->US_THR = v #define UART_GET_BRGR(port) ((AT91PS_USART)(port)->membase)->US_BRGR #define UART_PUT_BRGR(port,v) ((AT91PS_USART)(port)->membase)->US_BRGR = v +#define UART_PUT_RTOR(port,v) ((AT91PS_USART)(port)->membase)->US_RTOR = v // #define UART_GET_CR(port) ((AT91PS_USART)(port)->membase)->US_CR // is write-only + /* PDC registers */ +#define UART_PUT_PTCR(port,v) ((AT91PS_USART)(port)->membase)->US_PTCR = v +#define UART_PUT_RPR(port,v) ((AT91PS_USART)(port)->membase)->US_RPR = v +#define UART_PUT_RCR(port,v) ((AT91PS_USART)(port)->membase)->US_RCR = v +#define UART_GET_RCR(port) ((AT91PS_USART)(port)->membase)->US_RCR +#define UART_PUT_RNPR(port,v) ((AT91PS_USART)(port)->membase)->US_RNPR = v +#define UART_PUT_RNCR(port,v) ((AT91PS_USART)(port)->membase)->US_RNCR = v + static struct tty_driver normal, callout; static struct tty_struct *at91_table[AT91C_NR_UART]; static struct termios *at91_termios[AT91C_NR_UART], *at91_termios_locked[AT91C_NR_UART]; -static int (*at91_open)(struct uart_port *, struct uart_info *); -static void (*at91_close)(struct uart_port *, struct uart_info *); +static int (*at91_open)(struct uart_port *); +static void (*at91_close)(struct uart_port *); + +const int at91_serialmap[AT91C_NR_UART] = AT91C_UART_MAP; + +/* + * We wrap our port structure around the generic uart_port. + */ +struct at91_serial_port { + struct uart_port uart; +}; + +static struct at91_serial_port at91_ports[AT91C_NR_UART]; #ifdef SUPPORT_SYSRQ static struct console at91_console; @@ -92,15 +96,15 @@ /* * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. */ -static u_int at91_tx_empty(struct uart_port *port) +static u_int at91_tx_empty(struct uart_port *uart) { - return UART_GET_CSR(port) & AT91C_US_TXEMPTY ? TIOCSER_TEMT : 0; + return UART_GET_CSR(uart) & AT91C_US_TXEMPTY ? TIOCSER_TEMT : 0; } /* * Set state of the modem control output lines */ -static void at91_set_mctrl(struct uart_port *port, u_int mctrl) +static void at91_set_mctrl(struct uart_port *uart, u_int mctrl) { unsigned int control = 0; @@ -114,17 +118,17 @@ else control |= AT91C_US_DTRDIS; - UART_PUT_CR(port,control); + UART_PUT_CR(uart, control); } /* * Get state of the modem control input lines */ -static u_int at91_get_mctrl(struct uart_port *port) +static u_int at91_get_mctrl(struct uart_port *uart) { unsigned int status, ret = 0; - status = UART_GET_CSR(port); + status = UART_GET_CSR(uart); if (status & AT91C_US_DCD) ret |= TIOCM_CD; if (status & AT91C_US_CTS) @@ -140,70 +144,68 @@ /* * Stop transmitting. */ -static void at91_stop_tx(struct uart_port *port, u_int from_tty) +static void at91_stop_tx(struct uart_port *uart, u_int from_tty) { - UART_PUT_IDR(port, AT91C_US_TXRDY); - port->read_status_mask &= ~AT91C_US_TXRDY; + UART_PUT_IDR(uart, AT91C_US_TXRDY); + uart->read_status_mask &= ~AT91C_US_TXRDY; } /* * Start transmitting. */ -static void at91_start_tx(struct uart_port *port, u_int nonempty, u_int from_tty) +static void at91_start_tx(struct uart_port *uart, u_int from_tty) { - if (nonempty) { - unsigned long flags; + unsigned long flags; - local_irq_save(flags); - port->read_status_mask |= AT91C_US_TXRDY; - UART_PUT_IER(port, AT91C_US_TXRDY); - local_irq_restore(flags); - } + local_irq_save(flags); + uart->read_status_mask |= AT91C_US_TXRDY; + UART_PUT_IER(uart, AT91C_US_TXRDY); + local_irq_restore(flags); } /* * Stop receiving - port is in process of being closed. */ -static void at91_stop_rx(struct uart_port *port) +static void at91_stop_rx(struct uart_port *uart) { - UART_PUT_IDR(port, AT91C_US_RXRDY); + UART_PUT_IDR(uart, AT91C_US_RXRDY); } /* * Enable modem status interrupts */ -static void at91_enable_ms(struct uart_port *port) +static void at91_enable_ms(struct uart_port *uart) { - UART_PUT_IER(port, AT91C_US_RIIC | AT91C_US_DSRIC | AT91C_US_DCDIC | AT91C_US_CTSIC); + UART_PUT_IER(uart, AT91C_US_RIIC | AT91C_US_DSRIC | AT91C_US_DCDIC | AT91C_US_CTSIC); } /* * Control the transmission of a break signal */ -static void at91_break_ctl(struct uart_port *port, int break_state) +static void at91_break_ctl(struct uart_port *uart, int break_state) { if (break_state != 0) - UART_PUT_CR(port, AT91C_US_STTBRK); /* start break */ + UART_PUT_CR(uart, AT91C_US_STTBRK); /* start break */ else - UART_PUT_CR(port, AT91C_US_STPBRK); /* stop break */ + UART_PUT_CR(uart, AT91C_US_STPBRK); /* stop break */ } /* * Characters received (called from interrupt handler) */ -static void at91_rx_chars(struct uart_info *info, struct pt_regs *regs) +static void at91_rx_chars(struct at91_serial_port *port, struct pt_regs *regs) { - struct tty_struct *tty = info->tty; - struct uart_port *port = info->port; + struct uart_port *uart = &port->uart; + struct tty_struct *tty = uart->info->tty; unsigned int status, ch, flg, ignored = 0; - status = UART_GET_CSR(port); + status = UART_GET_CSR(uart); while (status & (AT91C_US_RXRDY)) { - ch = UART_GET_CHAR(port); + ch = UART_GET_CHAR(uart); if (tty->flip.count >= TTY_FLIPBUF_SIZE) goto ignore_char; - port->icount.rx++; + uart->icount.rx++; flg = TTY_NORMAL; @@ -214,7 +216,7 @@ if (status & (AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE)) goto handle_error; - if (uart_handle_sysrq_char(info, ch, regs)) + if (uart_handle_sysrq_char(uart, ch, regs)) goto ignore_char; error_return: @@ -222,7 +224,7 @@ *tty->flip.char_buf_ptr++ = ch; tty->flip.count++; ignore_char: - status = UART_GET_CSR(port); + status = UART_GET_CSR(uart); } out: tty_flip_buffer_push(tty); @@ -230,23 +232,23 @@ handle_error: if (status & (AT91C_US_PARE | AT91C_US_FRAME | AT91C_US_OVRE)) - UART_PUT_CR(port, AT91C_US_RSTSTA); /* clear error */ + UART_PUT_CR(uart, AT91C_US_RSTSTA); /* clear error */ if (status & (AT91C_US_PARE)) - port->icount.parity++; + uart->icount.parity++; else if (status & (AT91C_US_FRAME)) - port->icount.frame++; + uart->icount.frame++; if (status & (AT91C_US_OVRE)) - port->icount.overrun++; + uart->icount.overrun++; - if (status & port->ignore_status_mask) { + if (status & uart->ignore_status_mask) { if (++ignored > 100) goto out; goto ignore_char; } - status &= port->read_status_mask; + status &= uart->read_status_mask; - UART_PUT_CR(port, AT91C_US_RSTSTA); /* clear error */ + UART_PUT_CR(uart, AT91C_US_RSTSTA); /* clear error */ if (status & AT91C_US_PARE) flg = TTY_PARITY; else if (status & AT91C_US_FRAME) @@ -266,7 +268,7 @@ flg = TTY_OVERRUN; } #ifdef SUPPORT_SYSRQ - info->sysrq = 0; + uart->sysrq = 0; #endif goto error_return; } @@ -274,36 +276,36 @@ /* * Transmit characters (called from interrupt handler) */ -static void at91_tx_chars(struct uart_info *info) +static void at91_tx_chars(struct at91_serial_port *port) { - struct uart_port *port = info->port; + struct uart_port *uart = &port->uart; + struct circ_buf *xmit = &uart->info->xmit; - if (port->x_char) { - UART_PUT_CHAR(port, port->x_char); - port->icount.tx++; - port->x_char = 0; + if (uart->x_char) { + UART_PUT_CHAR(uart, uart->x_char); + uart->icount.tx++; + uart->x_char = 0; return; } - if (info->xmit.head == info->xmit.tail - || info->tty->stopped - || info->tty->hw_stopped) { - at91_stop_tx(info->port, 0); + + if (uart_circ_empty(xmit) || uart_tx_stopped(uart)) { + at91_stop_tx(uart, 0); return; } - while (UART_GET_CSR(port) & AT91C_US_TXRDY) { - UART_PUT_CHAR(port, info->xmit.buf[info->xmit.tail]); - info->xmit.tail = (info->xmit.tail + 1) & (UART_XMIT_SIZE - 1); - port->icount.tx++; - if (info->xmit.head == info->xmit.tail) + while (UART_GET_CSR(uart) & AT91C_US_TXRDY) { + UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + uart->icount.tx++; + if (uart_circ_empty(xmit)) break; } - if (CIRC_CNT(info->xmit.head, info->xmit.tail, UART_XMIT_SIZE) < WAKEUP_CHARS) - uart_event(info, EVT_WRITE_WAKEUP); + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(uart); - if (info->xmit.head == info->xmit.tail) - at91_stop_tx(info->port, 0); + if (uart_circ_empty(xmit)) + at91_stop_tx(uart, 0); } /* @@ -311,49 +313,50 @@ */ static void at91_interrupt(int irq, void *dev_id, struct pt_regs *regs) { - struct uart_info *info = dev_id; - struct uart_port *port = info->port; + struct at91_serial_port *port = dev_id; + struct uart_port *uart = &port->uart; unsigned int status, pending, pass_counter = 0; - status = UART_GET_CSR(port); - pending = status & port->read_status_mask; + status = UART_GET_CSR(uart); + pending = status & uart->read_status_mask; if (pending) { do { if (pending & AT91C_US_RXRDY) - at91_rx_chars(info, regs); + at91_rx_chars(port, regs); /* Clear the relevent break bits */ if (pending & AT91C_US_RXBRK) { - UART_PUT_CR(port, AT91C_US_RSTSTA); - port->icount.brk++; + UART_PUT_CR(uart, AT91C_US_RSTSTA); + uart->icount.brk++; #ifdef SUPPORT_SYSRQ - if (port->line == at91_console.index && !info->sysrq) { - info->sysrq = jiffies + HZ*5; + if (uart->line == at91_console.index && !uart->sysrq) { + uart->sysrq = jiffies + HZ*5; } #endif } // TODO: All reads to CSR will clear these interrupts! - if (pending & AT91C_US_RIIC) port->icount.rng++; - if (pending & AT91C_US_DSRIC) port->icount.dsr++; + if (pending & AT91C_US_RIIC) uart->icount.rng++; + if (pending & AT91C_US_DSRIC) uart->icount.dsr++; if (pending & AT91C_US_DCDIC) { - port->icount.dcd++; - uart_handle_dcd_change(info, status & AT91C_US_DCD); + uart->icount.dcd++; + uart_handle_dcd_change(uart, status & AT91C_US_DCD); } if (pending & AT91C_US_CTSIC) { - port->icount.cts++; - uart_handle_cts_change(info, status & AT91C_US_CTS); + uart->icount.cts++; + uart_handle_cts_change(uart, status & AT91C_US_CTS); } if (pending & (AT91C_US_RIIC | AT91C_US_DSRIC | AT91C_US_DCDIC | AT91C_US_CTSIC)) - wake_up_interruptible(&info->delta_msr_wait); + wake_up_interruptible(&uart->info->delta_msr_wait); if (pending & AT91C_US_TXRDY) - at91_tx_chars(info); + at91_tx_chars(port); + if (pass_counter++ > AT91_ISR_PASS_LIMIT) break; - status = UART_GET_CSR(port); - pending = status & port->read_status_mask; + status = UART_GET_CSR(uart); + pending = status & uart->read_status_mask; } while (pending); } } @@ -361,14 +364,14 @@ /* * Perform initialization and enable port for reception */ -static int at91_startup(struct uart_port *port, struct uart_info *info) +static int at91_startup(struct uart_port *uart) { int retval; /* * Allocate the IRQ */ - retval = request_irq(port->irq, at91_interrupt, SA_SHIRQ, "at91_serial", info); + retval = request_irq(uart->irq, at91_interrupt, SA_SHIRQ, "at91_serial", uart); if (retval) { printk("at91_serial: at91_startup - Can't get irq\n"); return retval; @@ -378,66 +381,68 @@ * control line interrupts) */ if (at91_open) { - retval = at91_open(port, info); + retval = at91_open(uart); if (retval) { - free_irq(port->irq, info); + free_irq(uart->irq, uart); return retval; } } /* Enable peripheral clock if required */ - if (port->irq != AT91C_ID_SYS) - AT91_SYS->PMC_PCER = 1 << port->irq; + if (uart->irq != AT91C_ID_SYS) + AT91_SYS->PMC_PCER = 1 << uart->irq; - port->read_status_mask = AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_OVRE + uart->read_status_mask = AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_OVRE | AT91C_US_FRAME | AT91C_US_PARE | AT91C_US_RXBRK; /* * Finally, clear and enable interrupts */ - UART_PUT_IDR(port, -1); - UART_PUT_CR(port, AT91C_US_TXEN | AT91C_US_RXEN); /* enable xmit & rcvr */ - UART_PUT_IER(port, AT91C_US_RXRDY); /* do receive only */ + UART_PUT_IDR(uart, -1); + UART_PUT_CR(uart, AT91C_US_TXEN | AT91C_US_RXEN); /* enable xmit & rcvr */ + UART_PUT_IER(uart, AT91C_US_RXRDY); /* do receive only */ return 0; } /* * Disable the port */ -static void at91_shutdown(struct uart_port *port, struct uart_info *info) +static void at91_shutdown(struct uart_port *uart) { /* * Free the interrupt */ - free_irq(port->irq, info); + free_irq(uart->irq, uart); /* * If there is a specific "close" function (to unregister * control line interrupts) */ if (at91_close) - at91_close(port, info); + at91_close(uart); /* * Disable all interrupts, port and break condition. */ - UART_PUT_CR(port, AT91C_US_RSTSTA); - UART_PUT_IDR(port, -1); + UART_PUT_CR(uart, AT91C_US_RSTSTA); + UART_PUT_IDR(uart, -1); /* Disable peripheral clock if required */ - if (port->irq != AT91C_ID_SYS) - AT91_SYS->PMC_PCDR = 1 << port->irq; + if (uart->irq != AT91C_ID_SYS) + AT91_SYS->PMC_PCDR = 1 << uart->irq; } +static struct uart_ops at91_pops; /* forward declaration */ + /* * Change the port parameters */ -static void at91_change_speed(struct uart_port *port, u_int cflag, u_int iflag, u_int quot) +static void at91_change_speed(struct uart_port *uart, u_int cflag, u_int iflag, u_int quot) { unsigned long flags; unsigned int mode, imr; /* Get current mode register */ - mode = UART_GET_MR(port) & ~(AT91C_US_CHRL | AT91C_US_NBSTOP | AT91C_US_PAR); + mode = UART_GET_MR(uart) & ~(AT91C_US_CHRL | AT91C_US_NBSTOP | AT91C_US_PAR); /* byte size */ switch (cflag & CSIZE) { @@ -461,7 +466,13 @@ /* parity */ if (cflag & PARENB) { - if (cflag & PARODD) + if (cflag & CMSPAR) { /* Mark or Space parity */ + if (cflag & PARODD) + mode |= AT91C_US_PAR_MARK; + else + mode |= AT91C_US_PAR_SPACE; + } + else if (cflag & PARODD) mode |= AT91C_US_PAR_ODD; else mode |= AT91C_US_PAR_EVEN; @@ -469,75 +480,79 @@ else mode |= AT91C_US_PAR_NONE; - port->read_status_mask |= AT91C_US_OVRE; + uart->read_status_mask |= AT91C_US_OVRE; if (iflag & INPCK) - port->read_status_mask |= AT91C_US_FRAME | AT91C_US_PARE; + uart->read_status_mask |= AT91C_US_FRAME | AT91C_US_PARE; if (iflag & (BRKINT | PARMRK)) - port->read_status_mask |= AT91C_US_RXBRK; + uart->read_status_mask |= AT91C_US_RXBRK; /* * Characters to ignore */ - port->ignore_status_mask = 0; + uart->ignore_status_mask = 0; if (iflag & IGNPAR) - port->ignore_status_mask |= (AT91C_US_FRAME | AT91C_US_PARE); + uart->ignore_status_mask |= (AT91C_US_FRAME | AT91C_US_PARE); if (iflag & IGNBRK) { - port->ignore_status_mask |= AT91C_US_RXBRK; + uart->ignore_status_mask |= AT91C_US_RXBRK; /* * If we're ignoring parity and break indicators, * ignore overruns too (for real raw support). */ if (iflag & IGNPAR) - port->ignore_status_mask |= AT91C_US_OVRE; + uart->ignore_status_mask |= AT91C_US_OVRE; } // TODO: Ignore all characters if CREAD is set. /* first, disable interrupts and drain transmitter */ local_irq_save(flags); - imr = UART_GET_IMR(port); /* get interrupt mask */ - UART_PUT_IDR(port, -1); /* disable all interrupts */ + imr = UART_GET_IMR(uart); /* get interrupt mask */ + UART_PUT_IDR(uart, -1); /* disable all interrupts */ local_irq_restore(flags); - while (!(UART_GET_CSR(port) & AT91C_US_TXEMPTY)) { barrier(); } + while (!(UART_GET_CSR(uart) & AT91C_US_TXEMPTY)) { barrier(); } /* disable receiver and transmitter */ - UART_PUT_CR(port, AT91C_US_TXDIS | AT91C_US_RXDIS); + UART_PUT_CR(uart, AT91C_US_TXDIS | AT91C_US_RXDIS); /* set the parity, stop bits and data size */ - UART_PUT_MR(port, mode); + UART_PUT_MR(uart, mode); /* set the baud rate */ - UART_PUT_BRGR(port, quot); - UART_PUT_CR(port, AT91C_US_TXEN | AT91C_US_RXEN); + UART_PUT_BRGR(uart, quot); + UART_PUT_CR(uart, AT91C_US_TXEN | AT91C_US_RXEN); /* restore interrupts */ - UART_PUT_IER(port, imr); + UART_PUT_IER(uart, imr); + + /* CTS flow-control and modem-status interrupts */ + if (UART_ENABLE_MS(uart, cflag)) + at91_pops.enable_ms(uart); } /* * Return string describing the specified port */ -static const char *at91_type(struct uart_port *port) +static const char *at91_type(struct uart_port *uart) { - return port->type == PORT_AT91RM9200 ? "AT91_SERIAL" : NULL; + return uart->type == PORT_AT91RM9200 ? "AT91_SERIAL" : NULL; } /* * Release the memory region(s) being used by 'port'. */ -static void at91_release_port(struct uart_port *port) +static void at91_release_port(struct uart_port *uart) { - release_mem_region(port->mapbase, - port->mapbase == AT91C_VA_BASE_DBGU ? 512 : SZ_16K); + release_mem_region(uart->mapbase, + uart->mapbase == AT91C_VA_BASE_DBGU ? 512 : SZ_16K); } /* * Request the memory region(s) being used by 'port'. */ -static int at91_request_port(struct uart_port *port) +static int at91_request_port(struct uart_port *uart) { - return request_mem_region(port->mapbase, - port->mapbase == AT91C_VA_BASE_DBGU ? 512 : SZ_16K, + return request_mem_region(uart->mapbase, + uart->mapbase == AT91C_VA_BASE_DBGU ? 512 : SZ_16K, "at91_serial") != NULL ? 0 : -EBUSY; } @@ -545,31 +560,31 @@ /* * Configure/autoconfigure the port. */ -static void at91_config_port(struct uart_port *port, int flags) +static void at91_config_port(struct uart_port *uart, int flags) { if (flags & UART_CONFIG_TYPE) { - port->type = PORT_AT91RM9200; - at91_request_port(port); + uart->type = PORT_AT91RM9200; + at91_request_port(uart); } } /* * Verify the new serial_struct (for TIOCSSERIAL). */ -static int at91_verify_port(struct uart_port *port, struct serial_struct *ser) +static int at91_verify_port(struct uart_port *uart, struct serial_struct *ser) { int ret = 0; if (ser->type != PORT_UNKNOWN && ser->type != PORT_AT91RM9200) ret = -EINVAL; - if (port->irq != ser->irq) + if (uart->irq != ser->irq) ret = -EINVAL; if (ser->io_type != SERIAL_IO_MEM) ret = -EINVAL; - if (port->uartclk / 16 != ser->baud_base) + if (uart->uartclk / 16 != ser->baud_base) ret = -EINVAL; - if ((void *)port->mapbase != ser->iomem_base) + if ((void *)uart->mapbase != ser->iomem_base) ret = -EINVAL; - if (port->iobase != ser->port) + if (uart->iobase != ser->port) ret = -EINVAL; if (ser->hub6 != 0) ret = -EINVAL; @@ -595,9 +610,26 @@ verify_port: at91_verify_port, }; -static struct uart_port at91_ports[AT91C_NR_UART]; +void __init at91_init_ports(void) +{ + static int first = 1; + int i; + + if (!first) + return; + first = 0; + + for (i = 0; i < AT91C_NR_UART; i++) { + at91_ports[i].uart.iotype = SERIAL_IO_MEM; + at91_ports[i].uart.flags = ASYNC_BOOT_AUTOCONF; + at91_ports[i].uart.uartclk = AT91C_MASTER_CLOCK; + at91_ports[i].uart.ops = &at91_pops; + at91_ports[i].uart.fifosize = 1; + at91_ports[i].uart.line = i; + } +} -void __init at91_register_uart_fns(struct at91_port_fns *fns) +void __init at91_register_uart_fns(struct at91rm9200_port_fns *fns) { if (fns->enable_ms) at91_pops.enable_ms = fns->enable_ms; @@ -621,41 +653,35 @@ return; } - at91_ports[idx].iotype = SERIAL_IO_MEM; - at91_ports[idx].flags = ASYNC_BOOT_AUTOCONF; - at91_ports[idx].uartclk = AT91C_MASTER_CLOCK; - at91_ports[idx].ops = &at91_pops; - at91_ports[idx].fifosize = 0; - switch (port) { case 0: - at91_ports[idx].membase = (void *) AT91C_VA_BASE_US0; - at91_ports[idx].mapbase = AT91C_VA_BASE_US0; - at91_ports[idx].irq = AT91C_ID_US0; + at91_ports[idx].uart.membase = (void *) AT91C_VA_BASE_US0; + at91_ports[idx].uart.mapbase = AT91C_VA_BASE_US0; + at91_ports[idx].uart.irq = AT91C_ID_US0; AT91_CfgPIO_USART0(); break; case 1: - at91_ports[idx].membase = (void *) AT91C_VA_BASE_US1; - at91_ports[idx].mapbase = AT91C_VA_BASE_US1; - at91_ports[idx].irq = AT91C_ID_US1; + at91_ports[idx].uart.membase = (void *) AT91C_VA_BASE_US1; + at91_ports[idx].uart.mapbase = AT91C_VA_BASE_US1; + at91_ports[idx].uart.irq = AT91C_ID_US1; AT91_CfgPIO_USART1(); break; case 2: - at91_ports[idx].membase = (void *) AT91C_VA_BASE_US2; - at91_ports[idx].mapbase = AT91C_VA_BASE_US2; - at91_ports[idx].irq = AT91C_ID_US2; + at91_ports[idx].uart.membase = (void *) AT91C_VA_BASE_US2; + at91_ports[idx].uart.mapbase = AT91C_VA_BASE_US2; + at91_ports[idx].uart.irq = AT91C_ID_US2; AT91_CfgPIO_USART2(); break; case 3: - at91_ports[idx].membase = (void *) AT91C_VA_BASE_US3; - at91_ports[idx].mapbase = AT91C_VA_BASE_US3; - at91_ports[idx].irq = AT91C_ID_US3; + at91_ports[idx].uart.membase = (void *) AT91C_VA_BASE_US3; + at91_ports[idx].uart.mapbase = AT91C_VA_BASE_US3; + at91_ports[idx].uart.irq = AT91C_ID_US3; AT91_CfgPIO_USART3(); break; case 4: - at91_ports[idx].membase = (void *) AT91C_VA_BASE_DBGU; - at91_ports[idx].mapbase = AT91C_VA_BASE_DBGU; - at91_ports[idx].irq = AT91C_ID_SYS; + at91_ports[idx].uart.membase = (void *) AT91C_VA_BASE_DBGU; + at91_ports[idx].uart.mapbase = AT91C_VA_BASE_DBGU; + at91_ports[idx].uart.irq = AT91C_ID_SYS; AT91_CfgPIO_DBGU(); break; default: @@ -665,37 +691,33 @@ #ifdef CONFIG_SERIAL_AT91_CONSOLE -#ifndef CONFIG_AT91_DEFAULT_BAUDRATE -#define CONFIG_AT91_DEFAULT_BAUDRATE 115200 -#endif - /* * Interrupts are disabled on entering */ static void at91_console_write(struct console *co, const char *s, u_int count) { - struct uart_port *port = at91_ports + co->index; + struct uart_port *uart = &at91_ports[co->index].uart; unsigned int status, i, imr; /* * First, save IMR and then disable interrupts */ - imr = UART_GET_IMR(port); /* get interrupt mask */ - UART_PUT_IDR(port, AT91C_US_RXRDY | AT91C_US_TXRDY); + imr = UART_GET_IMR(uart); /* get interrupt mask */ + UART_PUT_IDR(uart, AT91C_US_RXRDY | AT91C_US_TXRDY); /* * Now, do each character */ for (i = 0; i < count; i++) { do { - status = UART_GET_CSR(port); + status = UART_GET_CSR(uart); } while (!(status & AT91C_US_TXRDY)); - UART_PUT_CHAR(port, s[i]); + UART_PUT_CHAR(uart, s[i]); if (s[i] == '\n') { do { - status = UART_GET_CSR(port); + status = UART_GET_CSR(uart); } while (!(status & AT91C_US_TXRDY)); - UART_PUT_CHAR(port, '\r'); + UART_PUT_CHAR(uart, '\r'); } } @@ -704,9 +726,9 @@ * and restore IMR */ do { - status = UART_GET_CSR(port); + status = UART_GET_CSR(uart); } while (status & AT91C_US_TXRDY); - UART_PUT_IER(port, imr); /* set interrupts back the way they were */ + UART_PUT_IER(uart, imr); /* set interrupts back the way they were */ } static kdev_t at91_console_device(struct console *co) @@ -718,12 +740,12 @@ * If the port was already initialised (eg, by a boot loader), try to determine * the current setup. */ -static void __init at91_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits) +static void __init at91_console_get_options(struct uart_port *uart, int *baud, int *parity, int *bits) { unsigned int cr, mr, quot; // TODO: CR is a write-only register -// cr = UART_GET_CR(port) & (AT91C_US_RXEN | AT91C_US_TXEN); +// cr = UART_GET_CR(uart) & (AT91C_US_RXEN | AT91C_US_TXEN); // if (cr == (AT91C_US_RXEN | AT91C_US_TXEN)) { // /* ok, the port was enabled */ // @@ -736,20 +758,20 @@ // *parity = 'o'; // } - mr = UART_GET_MR(port) & AT91C_US_CHRL; + mr = UART_GET_MR(uart) & AT91C_US_CHRL; if (mr == AT91C_US_CHRL_8_BITS) *bits = 8; else *bits = 7; - quot = UART_GET_BRGR(port); - *baud = port->uartclk / (16 * (quot)); + quot = UART_GET_BRGR(uart); + *baud = uart->uartclk / (16 * (quot)); } static int __init at91_console_setup(struct console *co, char *options) { - struct uart_port *port; - int baud = CONFIG_AT91_DEFAULT_BAUDRATE; + struct uart_port *uart; + int baud = AT91C_CONSOLE_DEFAULT_BAUDRATE; int bits = 8; int parity = 'n'; int flow = 'n'; @@ -759,7 +781,9 @@ * if so, search for the first available port that does have * console support. */ - port = uart_get_console(at91_ports, AT91C_NR_UART, co); + if (co->index >= AT91C_NR_UART) + co->index = 0; + uart = &at91_ports[co->index].uart; // TODO: The console port should be initialized, and clock enabled if // we're not relying on the bootloader to do it. @@ -767,9 +791,9 @@ if (options) uart_parse_options(options, &baud, &parity, &bits, &flow); else - at91_console_get_options(port, &baud, &parity, &bits); + at91_console_get_options(uart, &baud, &parity, &bits); - return uart_set_options(port, co, baud, parity, bits, flow); + return uart_set_options(uart, co, baud, parity, bits, flow); } static struct console at91_console = { @@ -785,6 +809,7 @@ void __init at91_console_init(void) { + at91_init_ports(); register_console(&at91_console); } @@ -792,7 +817,7 @@ #define AT91_CONSOLE_DEVICE NULL #endif -static struct uart_driver at91_reg = { +static struct uart_driver at91_uart = { owner: THIS_MODULE, normal_major: SERIAL_AT91_MAJOR, #ifdef CONFIG_DEVFS_FS @@ -810,18 +835,37 @@ termios_locked: at91_termios_locked, minor: MINOR_START, nr: AT91C_NR_UART, - port: at91_ports, cons: AT91_CONSOLE_DEVICE, }; static int __init at91_serial_init(void) { - return uart_register_driver(&at91_reg); + int ret, i; + + at91_init_ports(); + + ret = uart_register_driver(&at91_uart); + if (ret) + return ret; + + for (i = 0; i < AT91C_NR_UART; i++) { + if (at91_serialmap[i] >= 0) + uart_add_one_port(&at91_uart, &at91_ports[i].uart); + } + + return 0; } static void __exit at91_serial_exit(void) { - uart_unregister_driver(&at91_reg); + int i; + + for (i = 0; i < AT91C_NR_UART; i++) { + if (at91_serialmap[i] >= 0) + uart_remove_one_port(&at91_uart, &at91_ports[i].uart); + } + + uart_unregister_driver(&at91_uart); } module_init(at91_serial_init); diff -urN linux-2.4.21-rmk2.orig/drivers/at91/spi/at91_spi.c linux-2.4.21-rmk2/drivers/at91/spi/at91_spi.c --- linux-2.4.21-rmk2.orig/drivers/at91/spi/at91_spi.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/spi/at91_spi.c Mon Mar 8 14:27:28 2004 @@ -171,7 +171,7 @@ /* * Handle interrupts from the SPI controller. */ -void spi_interrupt(int irq, void *dev_id, struct pt_regs *regs) +static void spi_interrupt(int irq, void *dev_id, struct pt_regs *regs) { unsigned int status; struct spi_local *device = (struct spi_local *) &spi_dev[current_device]; diff -urN linux-2.4.21-rmk2.orig/drivers/at91/spi/at91_spidev.c linux-2.4.21-rmk2/drivers/at91/spi/at91_spidev.c --- linux-2.4.21-rmk2.orig/drivers/at91/spi/at91_spidev.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/spi/at91_spidev.c Mon Mar 8 14:27:28 2004 @@ -112,7 +112,7 @@ return res; } -int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +static int spidev_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { int spi_device = MINOR(inode->i_rdev); @@ -131,7 +131,7 @@ /* * Open the SPI device */ -int spidev_open(struct inode *inode, struct file *file) +static int spidev_open(struct inode *inode, struct file *file) { unsigned int spi_device = MINOR(inode->i_rdev); @@ -205,7 +205,7 @@ /* * Remove the SPI /dev interface driver */ -static void at91_spidev_exit(void) +static void __exit at91_spidev_exit(void) { #ifdef CONFIG_DEVFS_FS devfs_unregister(devfs_handle); diff -urN linux-2.4.21-rmk2.orig/drivers/at91/watchdog/at91_wdt.c linux-2.4.21-rmk2/drivers/at91/watchdog/at91_wdt.c --- linux-2.4.21-rmk2.orig/drivers/at91/watchdog/at91_wdt.c Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/at91/watchdog/at91_wdt.c Mon Mar 8 14:27:28 2004 @@ -27,7 +27,7 @@ /* * Disable the watchdog. */ -void at91_wdt_stop(void) +static void at91_wdt_stop(void) { AT91_SYS->ST_WDMR = AT91C_ST_EXTEN; } @@ -35,7 +35,7 @@ /* * Enable and reset the watchdog. */ -void at91_wdt_start(void) +static void at91_wdt_start(void) { AT91_SYS->ST_WDMR = AT91C_ST_EXTEN | AT91C_ST_RSTEN | (((65536 * at91wdt_time) >> 8) & AT91C_ST_WDV); AT91_SYS->ST_CR = AT91C_ST_WDRST; diff -urN linux-2.4.21-rmk2.orig/drivers/char/ds1307.h linux-2.4.21-rmk2/drivers/char/ds1307.h --- linux-2.4.21-rmk2.orig/drivers/char/ds1307.h Mon Mar 8 14:25:56 2004 +++ linux-2.4.21-rmk2/drivers/char/ds1307.h Mon Mar 8 14:27:29 2004 @@ -11,7 +11,7 @@ #ifndef DS1307_H #define DS1307_H -#if defined(CONFIG_PXA_EMERSON_SBC) || defined(CONFIG_PXA_CERF_BOARD) +#if defined(CONFIG_PXA_EMERSON_SBC) || defined(CONFIG_PXA_CERF_BOARD) || defined(CONFIG_MACH_CSB337) #define DS1307_I2C_SLAVE_ADDR 0x68 #else #define DS1307_I2C_SLAVE_ADDR 0xffff diff -urN linux-2.4.21-rmk2.orig/drivers/mtd/nand/Config.in linux-2.4.21-rmk2/drivers/mtd/nand/Config.in --- linux-2.4.21-rmk2.orig/drivers/mtd/nand/Config.in Mon Mar 8 14:25:33 2004 +++ linux-2.4.21-rmk2/drivers/mtd/nand/Config.in Mon Mar 8 14:27:29 2004 @@ -33,4 +33,8 @@ fi fi +if [ "$CONFIG_ARCH_AT91RM9200" = "y" ]; then + dep_tristate ' SmartMedia Card on Atmel AT91RM9200' CONFIG_MTD_AT91_SMARTMEDIA $CONFIG_MTD_NAND +fi + endmenu diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/AT91RM9200.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/AT91RM9200.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/AT91RM9200.h Mon Mar 8 14:25:58 2004 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/AT91RM9200.h Mon Mar 8 14:27:29 2004 @@ -171,7 +171,7 @@ #define AT91C_PA23_TXD2 (AT91C_PIO_PA23) // USART 2 Transmit Data #define AT91C_PA23_IRQ3 (AT91C_PIO_PA23) // Interrupt input 3 #define AT91C_PIO_PA24 (1 << 24) -#define AT91C_PA24_SCK2 (AT91C_PIO_PA24) // USART2 Serial Clock +#define AT91C_PA24_SCK2 (AT91C_PIO_PA24) // USART 2 Serial Clock #define AT91C_PA24_PCK1 (AT91C_PIO_PA24) // PMC Programmable Clock Output 1 #define AT91C_PIO_PA25 (1 << 25) #define AT91C_PA25_TWD (AT91C_PIO_PA25) // TWI Two-wire Serial Data @@ -260,7 +260,7 @@ #define AT91C_PIO_PB21 (1 << 21) #define AT91C_PB21_RXD1 (AT91C_PIO_PB21) // USART 1 Receive Data #define AT91C_PIO_PB22 (1 << 22) -#define AT91C_PB22_SCK1 (AT91C_PIO_PB22) // USART1 Serial Clock +#define AT91C_PB22_SCK1 (AT91C_PIO_PB22) // USART 1 Serial Clock #define AT91C_PIO_PB23 (1 << 23) #define AT91C_PB23_DCD1 (AT91C_PIO_PB23) // USART 1 Data Carrier Detect #define AT91C_PIO_PB24 (1 << 24) diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_MCI.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/AT91RM9200_MCI.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_MCI.h Thu Jan 1 02:00:00 1970 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/AT91RM9200_MCI.h Mon Mar 8 14:27:29 2004 @@ -0,0 +1,127 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91RM9200.h +// Object : AT91RM9200 / MCI definitions +// Generated : AT91 SW Application Group 12/03/2002 (10:48:02) +// +// ---------------------------------------------------------------------------- + +#ifndef AT91RM9200_MCI_H +#define AT91RM9200_MCI_H + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Multimedia Card Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ + +typedef struct _AT91S_MCI { + AT91_REG MCI_CR; // MCI Control Register + AT91_REG MCI_MR; // MCI Mode Register + AT91_REG MCI_DTOR; // MCI Data Timeout Register + AT91_REG MCI_SDCR; // MCI SD Card Register + AT91_REG MCI_ARGR; // MCI Argument Register + AT91_REG MCI_CMDR; // MCI Command Register + AT91_REG Reserved0[2]; // + AT91_REG MCI_RSPR[4]; // MCI Response Register + AT91_REG MCI_RDR; // MCI Receive Data Register + AT91_REG MCI_TDR; // MCI Transmit Data Register + AT91_REG Reserved1[2]; // + AT91_REG MCI_SR; // MCI Status Register + AT91_REG MCI_IER; // MCI Interrupt Enable Register + AT91_REG MCI_IDR; // MCI Interrupt Disable Register + AT91_REG MCI_IMR; // MCI Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG MCI_RPR; // Receive Pointer Register + AT91_REG MCI_RCR; // Receive Counter Register + AT91_REG MCI_TPR; // Transmit Pointer Register + AT91_REG MCI_TCR; // Transmit Counter Register + AT91_REG MCI_RNPR; // Receive Next Pointer Register + AT91_REG MCI_RNCR; // Receive Next Counter Register + AT91_REG MCI_TNPR; // Transmit Next Pointer Register + AT91_REG MCI_TNCR; // Transmit Next Counter Register + AT91_REG MCI_PTCR; // PDC Transfer Control Register + AT91_REG MCI_PTSR; // PDC Transfer Status Register +} AT91S_MCI, *AT91PS_MCI; + +#endif + +// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- +#define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable +#define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable +#define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable +#define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable +// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- +#define AT91C_MCI_CLKDIV ((unsigned int) 0x1 << 0) // (MCI) Clock Divider +#define AT91C_MCI_PWSDIV ((unsigned int) 0x1 << 8) // (MCI) Power Saving Divider +#define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value +#define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode +#define AT91C_MCI_BLKLEN ((unsigned int) 0x1 << 18) // (MCI) Data Block Length +// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- +#define AT91C_MCI_DTOCYC ((unsigned int) 0x1 << 0) // (MCI) Data Timeout Cycle Number +#define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier +#define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1 +#define AT91C_MCI_DTOMUL_16 ((unsigned int) 0x1 << 4) // (MCI) DTOCYC x 16 +#define AT91C_MCI_DTOMUL_128 ((unsigned int) 0x2 << 4) // (MCI) DTOCYC x 128 +#define AT91C_MCI_DTOMUL_256 ((unsigned int) 0x3 << 4) // (MCI) DTOCYC x 256 +#define AT91C_MCI_DTOMUL_1024 ((unsigned int) 0x4 << 4) // (MCI) DTOCYC x 1024 +#define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096 +#define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536 +#define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576 +// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- +#define AT91C_MCI_SCDSEL ((unsigned int) 0x1 << 0) // (MCI) SD Card Selector +#define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width +// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- +#define AT91C_MCI_CMDNB ((unsigned int) 0x1F << 0) // (MCI) Command Number +#define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type +#define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response +#define AT91C_MCI_RSPTYP_48 ((unsigned int) 0x1 << 6) // (MCI) 48-bit response +#define AT91C_MCI_RSPTYP_136 ((unsigned int) 0x2 << 6) // (MCI) 136-bit response +#define AT91C_MCI_SPCMD ((unsigned int) 0x7 << 8) // (MCI) Special CMD +#define AT91C_MCI_SPCMD_NONE ((unsigned int) 0x0 << 8) // (MCI) Not a special CMD +#define AT91C_MCI_SPCMD_INIT ((unsigned int) 0x1 << 8) // (MCI) Initialization CMD +#define AT91C_MCI_SPCMD_SYNC ((unsigned int) 0x2 << 8) // (MCI) Synchronized CMD +#define AT91C_MCI_SPCMD_IT_CMD ((unsigned int) 0x4 << 8) // (MCI) Interrupt command +#define AT91C_MCI_SPCMD_IT_REP ((unsigned int) 0x5 << 8) // (MCI) Interrupt response +#define AT91C_MCI_OPDCMD ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command +#define AT91C_MCI_MAXLAT ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond +#define AT91C_MCI_TRCMD ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD +#define AT91C_MCI_TRCMD_NO ((unsigned int) 0x0 << 16) // (MCI) No transfer +#define AT91C_MCI_TRCMD_START ((unsigned int) 0x1 << 16) // (MCI) Start transfer +#define AT91C_MCI_TRCMD_STOP ((unsigned int) 0x2 << 16) // (MCI) Stop transfer +#define AT91C_MCI_TRDIR ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction +#define AT91C_MCI_TRTYP ((unsigned int) 0x3 << 19) // (MCI) Transfer Type +#define AT91C_MCI_TRTYP_BLOCK ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type +#define AT91C_MCI_TRTYP_MULTIPLE ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type +#define AT91C_MCI_TRTYP_STREAM ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type +// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- +#define AT91C_MCI_CMDRDY ((unsigned int) 0x1 << 0) // (MCI) Command Ready flag +#define AT91C_MCI_RXRDY ((unsigned int) 0x1 << 1) // (MCI) RX Ready flag +#define AT91C_MCI_TXRDY ((unsigned int) 0x1 << 2) // (MCI) TX Ready flag +#define AT91C_MCI_BLKE ((unsigned int) 0x1 << 3) // (MCI) Data Block Transfer Ended flag +#define AT91C_MCI_DTIP ((unsigned int) 0x1 << 4) // (MCI) Data Transfer in Progress flag +#define AT91C_MCI_NOTBUSY ((unsigned int) 0x1 << 5) // (MCI) Data Line Not Busy flag +#define AT91C_MCI_ENDRX ((unsigned int) 0x1 << 6) // (MCI) End of RX Buffer flag +#define AT91C_MCI_ENDTX ((unsigned int) 0x1 << 7) // (MCI) End of TX Buffer flag +#define AT91C_MCI_RXBUFF ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag +#define AT91C_MCI_TXBUFE ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag +#define AT91C_MCI_RINDE ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag +#define AT91C_MCI_RDIRE ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag +#define AT91C_MCI_RCRCE ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag +#define AT91C_MCI_RENDE ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag +#define AT91C_MCI_RTOE ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag +#define AT91C_MCI_DCRCE ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag +#define AT91C_MCI_DTOE ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag +#define AT91C_MCI_OVRE ((unsigned int) 0x1 << 30) // (MCI) Overrun flag +#define AT91C_MCI_UNRE ((unsigned int) 0x1 << 31) // (MCI) Underrun flag +// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- +// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- +// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- + +#endif diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_SSC.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/AT91RM9200_SSC.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_SSC.h Thu Jan 1 02:00:00 1970 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/AT91RM9200_SSC.h Mon Mar 8 14:27:29 2004 @@ -0,0 +1,129 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91RM9200.h +// Object : AT91RM9200 / SSC definitions +// Generated : AT91 SW Application Group 12/03/2002 (10:48:02) +// +// ---------------------------------------------------------------------------- + +#ifndef AT91RM9200_SSC_H +#define AT91RM9200_SSC_H + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ + +typedef struct _AT91S_SSC { + AT91_REG SSC_CR; // Control Register + AT91_REG SSC_CMR; // Clock Mode Register + AT91_REG Reserved0[2]; // + AT91_REG SSC_RCMR; // Receive Clock ModeRegister + AT91_REG SSC_RFMR; // Receive Frame Mode Register + AT91_REG SSC_TCMR; // Transmit Clock Mode Register + AT91_REG SSC_TFMR; // Transmit Frame Mode Register + AT91_REG SSC_RHR; // Receive Holding Register + AT91_REG SSC_THR; // Transmit Holding Register + AT91_REG Reserved1[2]; // + AT91_REG SSC_RSHR; // Receive Sync Holding Register + AT91_REG SSC_TSHR; // Transmit Sync Holding Register + AT91_REG SSC_RC0R; // Receive Compare 0 Register + AT91_REG SSC_RC1R; // Receive Compare 1 Register + AT91_REG SSC_SR; // Status Register + AT91_REG SSC_IER; // Interrupt Enable Register + AT91_REG SSC_IDR; // Interrupt Disable Register + AT91_REG SSC_IMR; // Interrupt Mask Register + AT91_REG Reserved2[44]; // + AT91_REG SSC_RPR; // Receive Pointer Register + AT91_REG SSC_RCR; // Receive Counter Register + AT91_REG SSC_TPR; // Transmit Pointer Register + AT91_REG SSC_TCR; // Transmit Counter Register + AT91_REG SSC_RNPR; // Receive Next Pointer Register + AT91_REG SSC_RNCR; // Receive Next Counter Register + AT91_REG SSC_TNPR; // Transmit Next Pointer Register + AT91_REG SSC_TNCR; // Transmit Next Counter Register + AT91_REG SSC_PTCR; // PDC Transfer Control Register + AT91_REG SSC_PTSR; // PDC Transfer Status Register +} AT91S_SSC, *AT91PS_SSC; + +#endif + +// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- +#define AT91C_SSC_RXEN ( 0x1 << 0) // (SSC) Receive Enable +#define AT91C_SSC_RXDIS ( 0x1 << 1) // (SSC) Receive Disable +#define AT91C_SSC_TXEN ( 0x1 << 8) // (SSC) Transmit Enable +#define AT91C_SSC_TXDIS ( 0x1 << 9) // (SSC) Transmit Disable +#define AT91C_SSC_SWRST ( 0x1 << 15) // (SSC) Software Reset +// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- +#define AT91C_SSC_CKS ( 0x3 << 0) // (SSC) Receive/Transmit Clock Selection +#define AT91C_SSC_CKS_DIV ( 0x0) // (SSC) Divided Clock +#define AT91C_SSC_CKS_TK ( 0x1) // (SSC) TK Clock signal +#define AT91C_SSC_CKS_RK ( 0x2) // (SSC) RK pin +#define AT91C_SSC_CKO ( 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection +#define AT91C_SSC_CKO_NONE ( 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only +#define AT91C_SSC_CKO_CONTINOUS ( 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output +#define AT91C_SSC_CKO_DATA_TX ( 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output +#define AT91C_SSC_CKI ( 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion +#define AT91C_SSC_CKG ( 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection +#define AT91C_SSC_CKG_NONE ( 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock +#define AT91C_SSC_CKG_LOW ( 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low +#define AT91C_SSC_CKG_HIGH ( 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High +#define AT91C_SSC_START ( 0xF << 8) // (SSC) Receive/Transmit Start Selection +#define AT91C_SSC_START_CONTINOUS ( 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. +#define AT91C_SSC_START_TX ( 0x1 << 8) // (SSC) Transmit/Receive start +#define AT91C_SSC_START_LOW_RF ( 0x2 << 8) // (SSC) Detection of a low level on RF input +#define AT91C_SSC_START_HIGH_RF ( 0x3 << 8) // (SSC) Detection of a high level on RF input +#define AT91C_SSC_START_FALL_RF ( 0x4 << 8) // (SSC) Detection of a falling edge on RF input +#define AT91C_SSC_START_RISE_RF ( 0x5 << 8) // (SSC) Detection of a rising edge on RF input +#define AT91C_SSC_START_LEVEL_RF ( 0x6 << 8) // (SSC) Detection of any level change on RF input +#define AT91C_SSC_START_EDGE_RF ( 0x7 << 8) // (SSC) Detection of any edge on RF input +#define AT91C_SSC_START_0 ( 0x8 << 8) // (SSC) Compare 0 +#define AT91C_SSC_STOP ( 0x1 << 12) // (SSC) Receive Stop Selection +#define AT91C_SSC_STTOUT ( 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection +#define AT91C_SSC_STTDLY ( 0xFF << 16) // (SSC) Receive/Transmit Start Delay +#define AT91C_SSC_PERIOD ( 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection +// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- +#define AT91C_SSC_DATLEN ( 0x1F << 0) // (SSC) Data Length +#define AT91C_SSC_LOOP ( 0x1 << 5) // (SSC) Loop Mode +#define AT91C_SSC_MSBF ( 0x1 << 7) // (SSC) Most Significant Bit First +#define AT91C_SSC_DATNB ( 0xF << 8) // (SSC) Data Number per Frame +#define AT91C_SSC_FSLEN ( 0xF << 16) // (SSC) Receive/Transmit Frame Sync length +#define AT91C_SSC_FSOS ( 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection +#define AT91C_SSC_FSOS_NONE ( 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only +#define AT91C_SSC_FSOS_NEGATIVE ( 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse +#define AT91C_SSC_FSOS_POSITIVE ( 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse +#define AT91C_SSC_FSOS_LOW ( 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer +#define AT91C_SSC_FSOS_HIGH ( 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer +#define AT91C_SSC_FSOS_TOGGLE ( 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer +#define AT91C_SSC_FSEDGE ( 0x1 << 24) // (SSC) Frame Sync Edge Detection +// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- +// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- +#define AT91C_SSC_DATDEF ( 0x1 << 5) // (SSC) Data Default Value +#define AT91C_SSC_FSDEN ( 0x1 << 23) // (SSC) Frame Sync Data Enable +// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- +#define AT91C_SSC_TXRDY ( 0x1 << 0) // (SSC) Transmit Ready +#define AT91C_SSC_TXEMPTY ( 0x1 << 1) // (SSC) Transmit Empty +#define AT91C_SSC_ENDTX ( 0x1 << 2) // (SSC) End Of Transmission +#define AT91C_SSC_TXBUFE ( 0x1 << 3) // (SSC) Transmit Buffer Empty +#define AT91C_SSC_RXRDY ( 0x1 << 4) // (SSC) Receive Ready +#define AT91C_SSC_OVRUN ( 0x1 << 5) // (SSC) Receive Overrun +#define AT91C_SSC_ENDRX ( 0x1 << 6) // (SSC) End of Reception +#define AT91C_SSC_RXBUFF ( 0x1 << 7) // (SSC) Receive Buffer Full +#define AT91C_SSC_CP0 ( 0x1 << 8) // (SSC) Compare 0 +#define AT91C_SSC_CP1 ( 0x1 << 9) // (SSC) Compare 1 +#define AT91C_SSC_TXSYN ( 0x1 << 10) // (SSC) Transmit Sync +#define AT91C_SSC_RXSYN ( 0x1 << 11) // (SSC) Receive Sync +#define AT91C_SSC_TXENA ( 0x1 << 16) // (SSC) Transmit Enable +#define AT91C_SSC_RXENA ( 0x1 << 17) // (SSC) Receive Enable +// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- +// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- +// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- + +#endif diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_TC.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/AT91RM9200_TC.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/AT91RM9200_TC.h Thu Jan 1 02:00:00 1970 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/AT91RM9200_TC.h Mon Mar 8 14:27:29 2004 @@ -0,0 +1,165 @@ +// ---------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +// ---------------------------------------------------------------------------- +// The software is delivered "AS IS" without warranty or condition of any +// kind, either express, implied or statutory. This includes without +// limitation any warranty or condition with respect to merchantability or +// fitness for any particular purpose, or against the infringements of +// intellectual property rights of others. +// ---------------------------------------------------------------------------- +// File Name : AT91RM9200.h +// Object : AT91RM9200 definitions +// Generated : AT91 SW Application Group 12/03/2002 (10:48:02) +// +// ---------------------------------------------------------------------------- + +#ifndef AT91RM9200_TC_H +#define AT91RM9200_TC_H + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface +// ***************************************************************************** +#ifndef __ASSEMBLY__ + +typedef struct _AT91S_TC { + AT91_REG TC_CCR; // Channel Control Register + AT91_REG TC_CMR; // Channel Mode Register + AT91_REG Reserved0[2]; // + AT91_REG TC_CV; // Counter Value + AT91_REG TC_RA; // Register A + AT91_REG TC_RB; // Register B + AT91_REG TC_RC; // Register C + AT91_REG TC_SR; // Status Register + AT91_REG TC_IER; // Interrupt Enable Register + AT91_REG TC_IDR; // Interrupt Disable Register + AT91_REG TC_IMR; // Interrupt Mask Register +} AT91S_TC, *AT91PS_TC; + +typedef struct _AT91S_TCB { + AT91S_TC TCB_TC0; // TC Channel 0 + AT91_REG Reserved0[4]; // + AT91S_TC TCB_TC1; // TC Channel 1 + AT91_REG Reserved1[4]; // + AT91S_TC TCB_TC2; // TC Channel 2 + AT91_REG Reserved2[4]; // + AT91_REG TCB_BCR; // TC Block Control Register + AT91_REG TCB_BMR; // TC Block Mode Register +} AT91S_TCB, *AT91PS_TCB; + +#endif + +// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- +#define AT91C_TC_CLKEN ( 0x1 << 0) // (TC) Counter Clock Enable Command +#define AT91C_TC_CLKDIS ( 0x1 << 1) // (TC) Counter Clock Disable Command +#define AT91C_TC_SWTRG ( 0x1 << 2) // (TC) Software Trigger Command +// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- +#define AT91C_TC_TCCLKS ( 0x7 << 0) // (TC) Clock Selection +#define AT91C_TC_TIMER_DIV1_CLOCK ( 0x0 << 0) // (TC) MCK/2 +#define AT91C_TC_TIMER_DIV2_CLOCK ( 0x1 << 0) // (TC) MCK/8 +#define AT91C_TC_TIMER_DIV3_CLOCK ( 0x2 << 0) // (TC) MCK/32 +#define AT91C_TC_TIMER_DIV4_CLOCK ( 0x3 << 0) // (TC) MCK/128 +#define AT91C_TC_TIMER_DIV5_CLOCK ( 0x4 << 0) // (TC) MCK/256 = SLOW CLOCK +#define AT91C_TC_TIMER_XC0 ( 0x5 << 0) // (TC) XC0 +#define AT91C_TC_TIMER_XC1 ( 0x6 << 0) // (TC) XC1 +#define AT91C_TC_TIMER_XC2 ( 0x7 << 0) // (TC) XC2 +#define AT91C_TC_CLKI ( 0x1 << 3) // (TC) Clock Invert +#define AT91C_TC_BURST ( 0x3 << 4) // (TC) Burst Signal Selection +#define AT91C_TC_CPCSTOP ( 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare +#define AT91C_TC_CPCDIS ( 0x1 << 7) // (TC) Counter Clock Disable with RC Compare +#define AT91C_TC_EEVTEDG ( 0x3 << 8) // (TC) External Event Edge Selection +#define AT91C_TC_EEVTEDG_NONE ( 0x0 << 8) // (TC) Edge: None +#define AT91C_TC_EEVTEDG_RISING ( 0x1 << 8) // (TC) Edge: rising edge +#define AT91C_TC_EEVTEDG_FALLING ( 0x2 << 8) // (TC) Edge: falling edge +#define AT91C_TC_EEVTEDG_BOTH ( 0x3 << 8) // (TC) Edge: each edge +#define AT91C_TC_EEVT ( 0x3 << 10) // (TC) External Event Selection +#define AT91C_TC_EEVT_NONE ( 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input +#define AT91C_TC_EEVT_RISING ( 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output +#define AT91C_TC_EEVT_FALLING ( 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output +#define AT91C_TC_EEVT_BOTH ( 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output +#define AT91C_TC_ENETRG ( 0x1 << 12) // (TC) External Event Trigger enable +#define AT91C_TC_WAVESEL ( 0x3 << 13) // (TC) Waveform Selection +#define AT91C_TC_WAVESEL_UP ( 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UP_AUTO ( 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN ( 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare +#define AT91C_TC_WAVESEL_UPDOWN_AUTO ( 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare +#define AT91C_TC_CPCTRG ( 0x1 << 14) // (TC) RC Compare Trigger Enable +#define AT91C_TC_WAVE ( 0x1 << 15) // (TC) +#define AT91C_TC_ACPA ( 0x3 << 16) // (TC) RA Compare Effect on TIOA +#define AT91C_TC_ACPA_NONE ( 0x0 << 16) // (TC) Effect: none +#define AT91C_TC_ACPA_SET ( 0x1 << 16) // (TC) Effect: set +#define AT91C_TC_ACPA_CLEAR ( 0x2 << 16) // (TC) Effect: clear +#define AT91C_TC_ACPA_TOGGLE ( 0x3 << 16) // (TC) Effect: toggle +#define AT91C_TC_ACPC ( 0x3 << 18) // (TC) RC Compare Effect on TIOA +#define AT91C_TC_ACPC_NONE ( 0x0 << 18) // (TC) Effect: none +#define AT91C_TC_ACPC_SET ( 0x1 << 18) // (TC) Effect: set +#define AT91C_TC_ACPC_CLEAR ( 0x2 << 18) // (TC) Effect: clear +#define AT91C_TC_ACPC_TOGGLE ( 0x3 << 18) // (TC) Effect: toggle +#define AT91C_TC_AEEVT ( 0x3 << 20) // (TC) External Event Effect on TIOA +#define AT91C_TC_AEEVT_NONE ( 0x0 << 20) // (TC) Effect: none +#define AT91C_TC_AEEVT_SET ( 0x1 << 20) // (TC) Effect: set +#define AT91C_TC_AEEVT_CLEAR ( 0x2 << 20) // (TC) Effect: clear +#define AT91C_TC_AEEVT_TOGGLE ( 0x3 << 20) // (TC) Effect: toggle +#define AT91C_TC_ASWTRG ( 0x3 << 22) // (TC) Software Trigger Effect on TIOA +#define AT91C_TC_ASWTRG_NONE ( 0x0 << 22) // (TC) Effect: none +#define AT91C_TC_ASWTRG_SET ( 0x1 << 22) // (TC) Effect: set +#define AT91C_TC_ASWTRG_CLEAR ( 0x2 << 22) // (TC) Effect: clear +#define AT91C_TC_ASWTRG_TOGGLE ( 0x3 << 22) // (TC) Effect: toggle +#define AT91C_TC_BCPB ( 0x3 << 24) // (TC) RB Compare Effect on TIOB +#define AT91C_TC_BCPB_NONE ( 0x0 << 24) // (TC) Effect: none +#define AT91C_TC_BCPB_SET ( 0x1 << 24) // (TC) Effect: set +#define AT91C_TC_BCPB_CLEAR ( 0x2 << 24) // (TC) Effect: clear +#define AT91C_TC_BCPB_TOGGLE ( 0x3 << 24) // (TC) Effect: toggle +#define AT91C_TC_BCPC ( 0x3 << 26) // (TC) RC Compare Effect on TIOB +#define AT91C_TC_BCPC_NONE ( 0x0 << 26) // (TC) Effect: none +#define AT91C_TC_BCPC_SET ( 0x1 << 26) // (TC) Effect: set +#define AT91C_TC_BCPC_CLEAR ( 0x2 << 26) // (TC) Effect: clear +#define AT91C_TC_BCPC_TOGGLE ( 0x3 << 26) // (TC) Effect: toggle +#define AT91C_TC_BEEVT ( 0x3 << 28) // (TC) External Event Effect on TIOB +#define AT91C_TC_BEEVT_NONE ( 0x0 << 28) // (TC) Effect: none +#define AT91C_TC_BEEVT_SET ( 0x1 << 28) // (TC) Effect: set +#define AT91C_TC_BEEVT_CLEAR ( 0x2 << 28) // (TC) Effect: clear +#define AT91C_TC_BEEVT_TOGGLE ( 0x3 << 28) // (TC) Effect: toggle +#define AT91C_TC_BSWTRG ( 0x3 << 30) // (TC) Software Trigger Effect on TIOB +#define AT91C_TC_BSWTRG_NONE ( 0x0 << 30) // (TC) Effect: none +#define AT91C_TC_BSWTRG_SET ( 0x1 << 30) // (TC) Effect: set +#define AT91C_TC_BSWTRG_CLEAR ( 0x2 << 30) // (TC) Effect: clear +#define AT91C_TC_BSWTRG_TOGGLE ( 0x3 << 30) // (TC) Effect: toggle +// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- +#define AT91C_TC_COVFS ( 0x1 << 0) // (TC) Counter Overflow +#define AT91C_TC_LOVRS ( 0x1 << 1) // (TC) Load Overrun +#define AT91C_TC_CPAS ( 0x1 << 2) // (TC) RA Compare +#define AT91C_TC_CPBS ( 0x1 << 3) // (TC) RB Compare +#define AT91C_TC_CPCS ( 0x1 << 4) // (TC) RC Compare +#define AT91C_TC_LDRAS ( 0x1 << 5) // (TC) RA Loading +#define AT91C_TC_LDRBS ( 0x1 << 6) // (TC) RB Loading +#define AT91C_TC_ETRCS ( 0x1 << 7) // (TC) External Trigger +#define AT91C_TC_ETRGS ( 0x1 << 16) // (TC) Clock Enabling +#define AT91C_TC_MTIOA ( 0x1 << 17) // (TC) TIOA Mirror +#define AT91C_TC_MTIOB ( 0x1 << 18) // (TC) TIOA Mirror +// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- +// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- +// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- + +// ***************************************************************************** +// SOFTWARE API DEFINITION FOR Timer Counter Interface +// ***************************************************************************** +// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- +#define AT91C_TCB_SYNC ( 0x1 << 0) // (TCB) Synchro Command +// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- +#define AT91C_TCB_TC0XC0S ( 0x1 << 0) // (TCB) External Clock Signal 0 Selection +#define AT91C_TCB_TC0XC0S_TCLK0 ( 0x0) // (TCB) TCLK0 connected to XC0 +#define AT91C_TCB_TC0XC0S_NONE ( 0x1) // (TCB) None signal connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA1 ( 0x2) // (TCB) TIOA1 connected to XC0 +#define AT91C_TCB_TC0XC0S_TIOA2 ( 0x3) // (TCB) TIOA2 connected to XC0 +#define AT91C_TCB_TC1XC1S ( 0x1 << 2) // (TCB) External Clock Signal 1 Selection +#define AT91C_TCB_TC1XC1S_TCLK1 ( 0x0 << 2) // (TCB) TCLK1 connected to XC1 +#define AT91C_TCB_TC1XC1S_NONE ( 0x1 << 2) // (TCB) None signal connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA0 ( 0x2 << 2) // (TCB) TIOA0 connected to XC1 +#define AT91C_TCB_TC1XC1S_TIOA2 ( 0x3 << 2) // (TCB) TIOA2 connected to XC1 +#define AT91C_TCB_TC2XC2S ( 0x1 << 4) // (TCB) External Clock Signal 2 Selection +#define AT91C_TCB_TC2XC2S_TCLK2 ( 0x0 << 4) // (TCB) TCLK2 connected to XC2 +#define AT91C_TCB_TC2XC2S_NONE ( 0x1 << 4) // (TCB) None signal connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA0 ( 0x2 << 4) // (TCB) TIOA0 connected to XC2 +#define AT91C_TCB_TC2XC2S_TIOA2 ( 0x3 << 4) // (TCB) TIOA2 connected to XC2 + +#endif diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/at91rm9200dk.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/at91rm9200dk.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/at91rm9200dk.h Mon Mar 8 14:25:58 2004 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/at91rm9200dk.h Mon Mar 8 14:27:29 2004 @@ -17,7 +17,7 @@ /* AT91RM92000 clocks */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ -#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ +#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MAIN_CLOCK / 3) */ #define AT91C_SLOW_CLOCK 32768 /* slow clock */ @@ -69,6 +69,8 @@ #define AT91_SMR_IRQ6 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (IRQ6) +#define AT91C_CONSOLE_DEFAULT_BAUDRATE 115200 /* default serial console baud-rate */ + /* * Serial port configuration. * 0 .. 3 = USART0 .. USART3 diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/csb337.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/csb337.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/csb337.h Thu Jan 1 02:00:00 1970 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/csb337.h Mon Mar 8 14:27:29 2004 @@ -0,0 +1,82 @@ +/* + * linux/include/asm-arm/arch-at91rm9200/csb337.h + * + * Copyright (c) 2003 Christopher Bahns & David Knickerbocker + * Polaroid Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_HARDWARE_CSB337_H +#define __ASM_ARCH_HARDWARE_CSB337_H + + +/* AT91RM92000 clocks on CSB337 */ +#define AT91C_MAIN_CLOCK 184320000 +#define AT91C_MASTER_CLOCK 46080000 /* peripheral clock (AT91C_MAIN_CLOCK / 4) */ +#define AT91C_SLOW_CLOCK 32768 /* slow clock */ + + +/* FLASH */ +#define AT91_FLASH_BASE 0x10000000 // NCS0: Flash physical base address + +/* SDRAM */ +#define AT91_SDRAM_BASE 0x20000000 // NCS1: SDRAM physical base address + +/* SmartMedia */ +#define AT91_SMARTMEDIA_BASE 0x40000000 // NCS3: Smartmedia physical base address + +/* Multi-Master Memory controller */ +#define AT91_UHP_BASE 0x00300000 // USB Host controller + + +/* Peripheral interrupt configuration */ +#define AT91_SMR_FIQ (AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (FIQ) +#define AT91_SMR_SYS (AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // System Peripheral +#define AT91_SMR_PIOA (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Parallel IO Controller A +#define AT91_SMR_PIOB (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Parallel IO Controller B +#define AT91_SMR_PIOC (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Parallel IO Controller C +#define AT91_SMR_PIOD (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Parallel IO Controller D +#define AT91_SMR_US0 (AT91C_AIC_PRIOR_6 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // USART 0 +#define AT91_SMR_US1 (AT91C_AIC_PRIOR_6 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // USART 1 +#define AT91_SMR_US2 (AT91C_AIC_PRIOR_6 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // USART 2 +#define AT91_SMR_US3 (AT91C_AIC_PRIOR_6 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // USART 3 +#define AT91_SMR_MCI (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Multimedia Card Interface +#define AT91_SMR_UDP (AT91C_AIC_PRIOR_4 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // USB Device Port +#define AT91_SMR_TWI (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Two-Wire Interface +#define AT91_SMR_SPI (AT91C_AIC_PRIOR_6 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Serial Peripheral Interface +#define AT91_SMR_SSC0 (AT91C_AIC_PRIOR_5 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Serial Synchronous Controller 0 +#define AT91_SMR_SSC1 (AT91C_AIC_PRIOR_5 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Serial Synchronous Controller 1 +#define AT91_SMR_SSC2 (AT91C_AIC_PRIOR_5 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Serial Synchronous Controller 2 +#define AT91_SMR_TC0 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Timer Counter 0 +#define AT91_SMR_TC1 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Timer Counter 1 +#define AT91_SMR_TC2 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Timer Counter 2 +#define AT91_SMR_TC3 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Timer Counter 3 +#define AT91_SMR_TC4 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Timer Counter 4 +#define AT91_SMR_TC5 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Timer Counter 5 +#define AT91_SMR_UHP (AT91C_AIC_PRIOR_3 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // USB Host port +#define AT91_SMR_EMAC (AT91C_AIC_PRIOR_3 | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Ethernet MAC +#define AT91_SMR_IRQ0 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (IRQ0) +#define AT91_SMR_IRQ1 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (IRQ1) +#define AT91_SMR_IRQ2 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (IRQ2) +#define AT91_SMR_IRQ3 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (IRQ3) +#define AT91_SMR_IRQ4 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (IRQ4) +#define AT91_SMR_IRQ5 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (IRQ5) +#define AT91_SMR_IRQ6 (AT91C_AIC_PRIOR_LOWEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE) // Advanced Interrupt Controller (IRQ6) + + +#define AT91C_CONSOLE_DEFAULT_BAUDRATE 38400 + +/* + * Serial port configuration. + * 0 .. 3 = USART0 .. USART3 + * 4 = DBGU + */ +#define AT91C_UART_MAP { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */ +#define AT91C_CONSOLE 0 /* ttyS0 */ + +#endif diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/hardware.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/hardware.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/hardware.h Mon Mar 8 14:25:58 2004 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/hardware.h Mon Mar 8 14:27:29 2004 @@ -60,6 +60,7 @@ #define AT91C_BASE_SRAM 0x00200000 /* Internal SRAM base address */ +#define AT91C_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */ #define AT91C_NR_UART 5 /* 4 USART3's and one DBGU port */ @@ -82,5 +83,9 @@ #include #endif +#ifdef CONFIG_MACH_CSB337 +#include +#endif + #endif diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/pio.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/pio.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/pio.h Mon Mar 8 14:25:58 2004 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/pio.h Mon Mar 8 14:27:29 2004 @@ -66,11 +66,23 @@ } /* + * Configure interrupt from Ethernet PHY. + */ +static inline void AT91_CfgPIO_EMAC_PHY(void) { + AT91_SYS->PMC_PCER = 1 << AT91C_ID_PIOC; /* enable peripheral clock */ +#ifdef CONFIG_MACH_CSB337 + AT91_SYS->PIOC_ODR = AT91C_PIO_PC2; +#else + AT91_SYS->PIOC_ODR = AT91C_PIO_PC4; +#endif +} + +/* * Enable the Two-Wire interface. */ static inline void AT91_CfgPIO_TWI(void) { - AT91_SYS->PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; AT91_SYS->PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK; + AT91_SYS->PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK; } /* diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/time.h linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/time.h --- linux-2.4.21-rmk2.orig/include/asm-arm/arch-at91rm9200/time.h Mon Mar 8 14:25:58 2004 +++ linux-2.4.21-rmk2/include/asm-arm/arch-at91rm9200/time.h Mon Mar 8 14:28:01 2004 @@ -27,6 +27,21 @@ extern unsigned long (*gettimeoffset)(void); /* + * The ST_CRTR is updated asynchronously to the master clock. It is therefore + * necessary to read it twice (with the same value) to ensure accuracy. + */ +static inline unsigned long read_CRTR(void) { + unsigned long x1, x2; + + do { + x1 = AT91_SYS->ST_CRTR; + x2 = AT91_SYS->ST_CRTR; + } while (x1 != x2); + + return x1; +} + +/* * Returns number of microseconds since last timer interrupt. Note that interrupts * will have been disabled by do_gettimeofday() * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy. @@ -36,7 +51,7 @@ { unsigned long elapsed; - elapsed = (AT91_SYS->ST_CRTR - AT91_SYS->ST_RTAR) & AT91C_ST_ALMV; + elapsed = (read_CRTR() - AT91_SYS->ST_RTAR) & AT91C_ST_ALMV; return (unsigned long)(elapsed * tick) / LATCH; } @@ -48,11 +63,12 @@ { if (AT91_SYS->ST_SR & AT91C_ST_PITS) { /* This is a shared interrupt */ do { + do_leds(); do_timer(regs); AT91_SYS->ST_RTAR = (AT91_SYS->ST_RTAR + LATCH) & AT91C_ST_ALMV; - } while (((AT91_SYS->ST_CRTR - AT91_SYS->ST_RTAR) & AT91C_ST_ALMV) >= LATCH); + } while (((read_CRTR() - AT91_SYS->ST_RTAR) & AT91C_ST_ALMV) >= LATCH); do_profile(regs); } diff -urN linux-2.4.21-rmk2.orig/include/asm-arm/mach/serial_at91rm9200.h linux-2.4.21-rmk2/include/asm-arm/mach/serial_at91rm9200.h --- linux-2.4.21-rmk2.orig/include/asm-arm/mach/serial_at91rm9200.h Mon Mar 8 14:25:58 2004 +++ linux-2.4.21-rmk2/include/asm-arm/mach/serial_at91rm9200.h Mon Mar 8 14:27:29 2004 @@ -10,7 +10,6 @@ #include struct uart_port; -struct uart_info; /* * This is a temporary structure for registering these @@ -22,11 +21,11 @@ void (*enable_ms)(struct uart_port *); void (*pm)(struct uart_port *, u_int, u_int); int (*set_wake)(struct uart_port *, u_int); - int (*open)(struct uart_port *, struct uart_info *); - void (*close)(struct uart_port *, struct uart_info *); + int (*open)(struct uart_port *); + void (*close)(struct uart_port *); }; -#if defined(CONFIG_SERIAL_AT91RM9200) +#if defined(CONFIG_SERIAL_AT91) void at91rm9200_register_uart_fns(struct at91rm9200_port_fns *fns); void at91rm9200_register_uart(int idx, int port); #else